Experimental facts about noise are presented which help us to understand the correlation between noise in a device and its reliability. The main advantages of noise measurements are that the tests are less destructive, faster and more sensitive than DC measurements after accelerated life tests. The following topics are addressed: 1) the kind of noise spectra in view of reliability diagnostics such as thermal noise, shot noise, the typical poor-device indicators like burst noise and generation-recombination noise and the 1/f/sup 2/ and 1/f noise; 2) why conduction noise is a quality indicator; 3) the quality of electrical contacts and vias; 4) electromigration damage; 5) the reliability in diode type devices like solar cells, laser diodes, and bipolar transistors; and 6) the series resistance in modern short channel MESFET, MODFET, and MOST devices. >

/pdf/noise-as-a-diagnostic-tool-for-quality-and-reliability-of-3vrnkdk5vf.pdf

Noise as a diagnostic tool for quality and reliability of electronic devices

P-channel LDD MOSFETs with a p+-poly gate and an n+-poly gate are investigated. The p+-poly gate forms a surface channel and the n+-pol gate a bulk channel. A new method is proposed to use an L-array for extracting the low field mobility μ00, the mobility degradation coefficient θ, the channel length correction l′, and the parameters Rs0 and Rsv for the gate-voltage-dependent series resistance on the source side RsS = Rs0 + Rsv/VG∗. A bulk channel device has a higher μ00 value, a Rsv and a smaller series resistance RDd on the drain side than a surface channel device. The θ value and the gate-voltage-independent part of the series resistance Rs0 are about the same in both devices. Under the same external bias conditions, a surface channel MOSFET has a smaller current and a higher 1/f current noise than a bulk channel device. The 1/f noise parameter α is found to be independent of the effective gate voltage and of the channel length for both defices. The bulk channel MOSFET shows α values of about 4×10−7 which are among the lowest values ever reported in literature. The α values in the surface channel devices are about two orders of magnitude higher than those in the bulk type. Comparing the d.c. characteristics and 1/f noise of both devices, an indication is given on how to reduce the 1/f noise in a surface p-channel MOSFET.

Parameter extraction and 1/f noise in a surface and a bulk-type p-channel LDD MOSFET

A unified and computationally efficient SPICE model for accurate prediction of the I-V characteristics of small-geometry lightly doped drain (LDD) MOSFETs is described. It is based on the enhancement of the SPICE LEVEL3 MOS model and a novel parameter extraction method. It supports the design of both short-channel and narrow-gate-width LDD MOSFETs with any kind of channel or field implant. A semiempirical approach to the modeling of the threshold voltage of LDD MOSFETs, in which the small-geometry effect is implemented, is demonstrated. The model is applicable to LDD MOSFETs with effective channel lengths and channel widths down to the submicrometer range and nonuniformity doped substrate. An LDD device is considered to be an intrinsic MOSFET in series with two external resistors. These two resistors account for the drain-to-source series resistance effect and are functions of drain-source voltage in the linear device-operating region. In addition, automatic extraction of device parameters for SPICE built-in LDD MOSFET models has been developed. Comparisons between the measured and modeled threshold voltages and I-V characteristics show excellent agreement for a wide range of channel lengths, widths and biases. >

https://ir.nctu.edu.tw:443/bitstream/11536/4298/1/A1989AL12900021.pdf

An efficient semi-empirical model of the I-V characteristics for LDD MOSFETS

This paper presents a novel approach for RF power measurements using a silicon MOSFET. It describes linear and nonlinear models of the RF MOSFET for results prediction. It shows a thorough comparison between predicted and measured results. The detector demonstrates a better sensitivity than biased Schottky diode detectors that we have measured.

RF power detector using a silicon MOSFET

An analytic saturation model for conventional and lightly doped drain (LDD) MOSFETs is developed by using the pseudo-two-dimensional approximation in the channel and drain regions to obtain both the channel length modulation factor and the maximum electric field. Using the established I-V model in the linear region, the drain currents of conventional and LDD MOSFETs can be explicitly calculated. The substrate currents of conventional/LDD MOSFETs are calculated by using an existing simplified substrate current formula and the maximum electric field model. It is shown that the accuracy of the maximum electric field is acceptable for calculating the substrate currents of conventional/LDD MOSFETs. The parameters used in the model can be determined by the existing extraction methods and the optimization technique. The saturation model is shown to be valid for a wide range of channel lengths and bias conditions. >

https://ir.nctu.edu.tw:443/bitstream/11536/4069/1/A1990DK33200009.pdf

An analytic saturation model for drain and substrate currents of conventional and LDD MOSFETs

An analytic I-V model for lightly doped drain (LDD) MOSFET devices is presented. In this model, the n-region is considered to be a modified buried-channel MOSFET device, and the channel region is considered to be an intrinsic enhancement-mode MOSFET device. Combining the models of these two regions, the drain current in the linear/saturation regions and the saturation voltage can be calculated directly from the terminal voltages. In addition, the parameters used in the channel region can be extracted by a series of least square fittings. According to comparisons between the experimental data measured from the test transistors and the theoretical calculations, the developed I-V model is shown to be valid for wide ranges of channel lengths.

https://ir.nctu.edu.tw:443/bitstream/11536/4639/1/A1987H779400012.pdf

Ching-Yuan Wu

Papers

An analytic I—V model for lightly doped drain (LDD) MOSFET devices

Ching-Yuan Wu

Papers

An analytic I&#8212;V model for lightly doped drain (LDD) MOSFET devices

An analytic I—V model for lightly doped drain (LDD) MOSFET devices