Advances in copper complexes as anticancer agents.

Noble metals in medicine: Latest advances

The multinational, distributed, and multistep nature of integrated circuit (IC) production supply chain has introduced hardware-based vulnerabilities. Existing literature in hardware security assumes ad hoc threat models, defenses, and metrics for evaluation, making it difficult to analyze and compare alternate solutions. This paper systematizes the current knowledge in this emerging field, including a classification of threat models, state-of-the-art defenses, and evaluation metrics for important hardware-based attacks.

A Primer on Hardware Security: Models, Methods, and Metrics

Domain-specific hardware is becoming a promising topic in the backdrop of improvement slow down for general-purpose processors due to the foreseeable end of Moore’s Law. Machine learning, especially deep neural networks (DNNs), has become the most dazzling domain witnessing successful applications in a wide spectrum of artificial intelligence (AI) tasks. The incomparable accuracy of DNNs is achieved by paying the cost of hungry memory consumption and high computational complexity, which greatly impedes their deployment in embedded systems. Therefore, the DNN compression concept was naturally proposed and widely used for memory saving and compute acceleration. In the past few years, a tremendous number of compression techniques have sprung up to pursue a satisfactory tradeoff between processing efficiency and application accuracy. Recently, this wave has spread to the design of neural network accelerators for gaining extremely high performance. However, the amount of related works is incredibly huge and the reported approaches are quite divergent. This research chaos motivates us to provide a comprehensive survey on the recent advances toward the goal of efficient compression and execution of DNNs without significantly compromising accuracy, involving both the high-level algorithms and their applications in hardware design. In this article, we review the mainstream compression approaches such as compact model, tensor decomposition, data quantization, and network sparsification. We explain their compression principles, evaluation metrics, sensitivity analysis, and joint-way use. Then, we answer the question of how to leverage these methods in the design of neural network accelerators and present the state-of-the-art hardware architectures. In the end, we discuss several existing issues such as fair comparison, testing workloads, automatic compression, influence on security, and framework/hardware-level support, and give promising topics in this field and the possible challenges as well. This article attempts to enable readers to quickly build up a big picture of neural network compression and acceleration, clearly evaluate various methods, and confidently get started in the right way.

Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey

Buildings are among the largest consumers of electricity in the US. A significant portion of this energy use in buildings can be attributed to HVAC systems used to maintain comfort for occupants. In most cases these building HVAC systems run on fixed schedules and do not employ any fine grained control based on detailed occupancy information. In this paper we present the design and implementation of a presence sensor platform that can be used for accurate occupancy detection at the level of individual offices. Our presence sensor is low-cost, wireless, and incrementally deployable within existing buildings. Using a pilot deployment of our system across ten offices over a two week period we identify significant opportunities for energy savings due to periods of vacancy. Our energy measurements show that our presence node has an estimated battery lifetime of over five years, while detecting occupancy accurately. Furthermore, using a building simulation framework and the occupancy information from our testbed, we show potential energy savings from 10% to 15% using our system.

[ACM Press the 2nd ACM Workshop - Zurich, Switzerland (2010.11.02-2010.11.02)] Proceedings of the 2nd ACM Workshop on Embedded Sensing Systems for Energy-Efficiency in Building - BuildSys \'10 - Occupancy-driven energy management for smart building automation

Traditionally, the only standard method of testing that has consistently provided high fault coverage has been scan test due to the high controllability and high observability this technique provides. The scan chains used in scan test not only allow test engineers to control and observe a chip, but these properties also allow the scan architecture to be used as a means to breach chip security. In this paper, we propose a technique, called Lock & Key, to neutralize the potential for scan-based side-channel attacks. It is very difficult to implement an all inclusive security strategy, but by knowing the attacker, a suitable strategy can be devised. The Lock & Key technique provides a flexible security strategy to modern designs without significant changes to scan test practices. Using this technique, the scan chains are divided into smaller subchains. With the inclusion of a test security controller, access to subchains are randomized when being accessed by an unauthorized user. Random access reduces repeatability and predictability making reverse engineering more difficult. Without proper authorization, an attacker would need to unveil several layers of security before gaining proper access to the scan chain in order to exploit it. The proposed Lock & Key technique is design independent while maintaining a relatively low area overhead.

Securing Designs against Scan-Based Side-Channel Attacks

Scan test has been a common and useful method for testing VLSI designs due to the high controllability and observability it provides. These same properties have recently been shown to also be a security threat to the intellectual property on a chip (Yang et al., 2004). In order to defend from scan based attacks, we present the lock & key technique. Our proposed technique provides security while not negatively impacting the design's fault coverage. This technique requires only that a small area overhead penalty is incurred for a significant return in security. Lock & key divides the already present scan chain into smaller subchains of equal length that are controlled by an internal test security controller. When a malicious user attempts to manipulate the scan chain, the test security controller goes into insecure mode and enables each subchain in an unpredictable sequence making controllability and observability of the circuit under test very difficult. We present and analyze the design of the lock & key techniques to show that this is a flexible option to secure scan designs for various levels of security

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Securing Scan Design Using Lock and Key Technique

A wireless sensor network deployed in an area of interest is affected by variations in environmental conditions associated with that area. It must adapt to these variations in order to continue functioning as desired by the user. We present a novel, two-phase solution to the wireless sensor network adaptivity problem. In the first phase, nodes in the network, organized as clusters, execute an efficient algorithm to dynamically calibrate sensed data. Each node provides its current energy level and the state of each on-board sensor to a cluster-head. In the second phase, each cluster-head executes an efficient, ontology-driven algorithm to determine the future state of the network under existing conditions, based on information received from each sensor node. We describe an example application scenario to show how our two-phase solution can be employed to enable a real-world wireless sensor network to adapt itself to variations in environmental conditions.

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Ontology-driven adaptive sensor networks

Cytotoxic, antibacterial, DNA interaction and superoxide dismutase like activities of sparfloxacin drug based copper(II) complexes with nitrogen donor ligands.

Home automation and environmental control is a key ingredient of smart homes. While systems for home automation and control exist, there are few systems that interact with individuals suffering from paralysis, paresis, weakness and limited range of motion that are common sequels resulting from severe injuries such as stroke, brain injury, spinal cord injury and many chronic (guillian barre syndrome) and degenerative (amyotrophic lateral sclerosis) conditions. To address this problem, we present the design, implementation, and evaluation of Inviz, a low-cost gesture recognition system for paralysis patients that uses flexible textile-based capacitive sensor arrays for movement detection. The design of Inviz presents two novel research contributions. First, the system uses flexible textile-based capacitive arrays as proximity sensors that are minimally obtrusive and can be built into clothing for gesture and movement detection in patients with limited body motion. The proximity sensing obviates the need for touch-based gesture recognition that can cause skin abrasion in paralysis patients, and the array of capacitive sensors help provide better spatial resolution and noise cancellation. Second, Inviz uses a low-power hierarchical signal processing algorithm that breaks down computation into multiple low and high power tiers. The tiered approach provides maximal vigilance at minimal energy consumption. We have designed and implemented a fully functional prototype of Inviz and we evaluate it in the context of an end-to-end home automation system and show that it achieves high accuracy while maintaining low latency and low energy consumption.

/pdf/inviz-low-power-personalized-gesture-recognition-using-1e0exskr3s.pdf

Chintan Patel

Papers

Securing Designs against Scan-Based Side-Channel Attacks

Securing Scan Design Using Lock and Key Technique

Ontology-driven adaptive sensor networks

Cytotoxic, antibacterial, DNA interaction and superoxide dismutase like activities of sparfloxacin drug based copper(II) complexes with nitrogen donor ligands.

Inviz: Low-power personalized gesture recognition using wearable textile capacitive sensor arrays