An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first metal electrode, a first antifuse dielectric layer, preferably silicon nitride, disposed on the lower first electrode and an antifuse layer, preferably amorphous silicon, disposed on the first dielectric layer. An inter-layer dielectric layer is disposed on the antifuse layer and includes an antifuse via formed completely therethrough. A second antifuse dielectric layer, preferably silicon nitride, is disposed over the amorphous silicon layer in the antifuse via, and an upper second metal electrode is disposed over the second dielectric layer in the antifuse via.

Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

The present invention relates to a high performance, high reliability antifuse using conductive electrodes. The problem of switch-off of the programmed antifuses is solved by reducing the thermal conductivity of the conductive electrodes. This is achieved by using lower thermal conductivity conductors for the electrodes or by using thinner electrodes to increase thermal resistance. According to a first aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials. According to a second aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing relatively thin electrodes, thus increasing their thermal resistance. According to a third aspect of the present invention, a relatively thin barrier layer is placed between one or both of the low thermal conductivity electrodes and the antifuse material in order to prevent reaction between the conductive electrodes and the antifuse material or the materials used in manufacturing such as the etch gas. According to a fourth aspect of the present invention low thermal conductivity conductors are used for both electrodes in the conductor-to-conductor antifuse in order to achieve enhanced reliability and freedom from switch-off. According to a fifth aspect of the present invention switch-off is cured in conductor-to-conductor antifuses without compromising low on-state resistance of the antifuse.

Antifuse structure suitable for VLSI application

A programmable interconnect device particularly suitable for field programmable ROM, field programmable gate array and field programmable microprocessor code, includes an intrinsic polycrystalline antifuse dielectric layer.

Programmable interconnect device and method of manufacturing same

A memory cell device having circuitry located between memory cell arrays comprises power and ground lines to the circuitry formed directly above the memory cell arrays. The power and ground lines are parallel and positioned in an adjacent alternating pattern such that a power line is positioned adjacent a ground line, which is positioned adjacent another power line and so on. Signal lines carrying signals to and from the circuitry are also formed directly above memory cell arrays.

Power and signal line bussing method for memory devices

Method for manufacturing polycrystalline silicon having high resistance, having a first step for depositing a polycrystalline silicon layer for a resistor area over a silicon semiconductor substrate; a second step for growing a first thermal oxide layer having a first specified depth over the polycrystalline silicon layer, ion-implanting with the nitrogen thereon, and growing a second thermal oxide layer having a second specified depth on the ion-implanted layer; a third step for forming a resistor pattern of the polycrystalline silicon with a photo etching method; and a fourth step for ion-implanting impurities in order to decrease the resistance of the polycrystalline silicon as contact regions to be used in resistance contacts with a fixed semiconductor region on the substrate.

Method for manufacturing poly-crystal sillicon having high resistance

Method of manufacturing high resistance polycrystalline silicon

Polycrystalline silicon 15 for a resistor is deposited using a chemical vapour deposition (CVD) method over a silicon substrate 10, upon which is formed field oxide 11, gate oxide 12 and a polycrystalline silicon gate 13. A first thermal oxide layer 17 is formed on the polycrystalline layer 15. The surface of the first thermal oxide layer 17 is then subjected to nitrogen ion-implantation. Following ion-implantation a second thermal oxide layer is formed. The polycrystalline layer 15 and the implanted nitrogen react together to form a high resistance layer of nitride component. It is found that the resistance of the polycrystalline silicon is dependent upon the amount of the nitride component, and a high value of resistance may be achieved. Instead of nitrogen, carbon, fluorine, chlorine, bromine, iodine, neon, argon, krypton, xenon or oxygen may be used. The invention may be of utility in highly-integrated SRAM devices which use high resistance polycrystalline silicon as a resistance material.

Choi Kyu-Hyun

Papers

Programmable interconnect device and method of manufacturing same

Power and signal line bussing method for memory devices

Method for manufacturing poly-crystal sillicon having high resistance

Method of manufacturing high resistance polycrystalline silicon

Verfahren zur herstellung von polykristallinem silizium mit hohem widerstandswert