An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Self-aligning contact and interconnect structure

A method of fabricating MOSFET device with polycide gate, which includes a polysilicon layer and a refractory metal silicide layer, is described. After a thin oxide layer is formed by a thermal process, the refractory metal silicide layer is transformed from an amorphous form to a crystalline form that leads to peeling and surface roughness problems in the prior art. This method utilizes an additional ion implantation step to transform the refractory metal silicide layer from the crystalline form back into the amorphous form. Hence, the problems of peeling and surface roughness of the polycide gate can be overcome.

Method for fabricating polycide gate MOSFET devices

A process for forming low resistance contacts between silicide areas and upper level polysilicon interconnect layers including a specific doping technique that provides solid low resistance contacts between a lower level of a silicided area and an upper level polysilicon interconnect. The doping technique combines a doping implant of the upper level polysilicon and an ion-mixing implant into a single implant thereby achieving a low resistive implant which also reduces processing steps.

Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects

A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the polycide peeling problems. A pattern of gate electrode structures is formed upon a semiconductor substrate which each includes a gate oxide, a polysilicon layer and an amorphous refractory metal silicide. The resulting structure may be annealed in oxygen at this time to change the refractory metal silicide from it deposited amorphous phase into its crystalline phase. This causes the formation of a thin layer of silicon dioxide upon the exposed silicon substrate, the exposed polysilicon layer and the exposed metal silicide layer. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric layer is blanket deposited over the surfaces and spacer structures formed by anisotropic etching. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The silicon oxide layer on the top surface of the metal silicate layer was removed by etching. Silicon ions are now implanted into the metal silicide layer to supply an excess of silicon ions at the surface of the metal silicide layer. The integrated circuit device is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover.

Peeling free metal silicide films using ion implantation

A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. There is then formed upon the oxygen containing plasma etchable microelectronics layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while employing the patterned photoresist layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching a hard mask material from which is formed the hard mask layer. There is then etched through use of a second plasma etch method the patterned photoresist layer from the patterned hard mask layer while employing the patterned hard mask layer as an etch stop layer while simultaneously etching the oxygen containing plasma etchable microelectronics layer while employing at least the patterned hard mask layer as a second etch mask layer to form a patterned oxygen containing plasma etchable microelectronics layer. The second plasma etch method employs an oxygen containing etchant gas composition. The method is particularly useful for forming patterned oxygen containing plasma etchable microelectronics dielectric layers within microelectronics fabrications.

Hard masking method for forming patterned oxygen containing plasma etchable layer

A method being capable of achieving the reduction in contact resistance between each layer when bringing a silicide layer into contact with a polycrystalline-silicon (polysilicon) layer in the manufacture of semiconductor devices. The method comprises the steps of forming a polysilicon layer and a silicide layer thereon over a partial top surface of a semiconductor substrate, forming an insulating layer over said silicide layer and the entire top surface of the substrate, forming a contact window by etching the partial area of the insulating layer over said silicide layer, and forming a polysilicon layer over the entire top surface of the substrate after performing ion-implantation through said contact window, wherein said ion-implantation is performed with N-type high doping into the silicide.

Method of making semiconductor devices having ohmic contact

Method for manufacturing polycrystalline silicon having high resistance, having a first step for depositing a polycrystalline silicon layer for a resistor area over a silicon semiconductor substrate; a second step for growing a first thermal oxide layer having a first specified depth over the polycrystalline silicon layer, ion-implanting with the nitrogen thereon, and growing a second thermal oxide layer having a second specified depth on the ion-implanted layer; a third step for forming a resistor pattern of the polycrystalline silicon with a photo etching method; and a fourth step for ion-implanting impurities in order to decrease the resistance of the polycrystalline silicon as contact regions to be used in resistance contacts with a fixed semiconductor region on the substrate.

Method of manufacturing high resistance polycrystalline silicon

Polycrystalline silicon 15 for a resistor is deposited using a chemical vapour deposition (CVD) method over a silicon substrate 10, upon which is formed field oxide 11, gate oxide 12 and a polycrystalline silicon gate 13. A first thermal oxide layer 17 is formed on the polycrystalline layer 15. The surface of the first thermal oxide layer 17 is then subjected to nitrogen ion-implantation. Following ion-implantation a second thermal oxide layer is formed. The polycrystalline layer 15 and the implanted nitrogen react together to form a high resistance layer of nitride component. It is found that the resistance of the polycrystalline silicon is dependent upon the amount of the nitride component, and a high value of resistance may be achieved. Instead of nitrogen, carbon, fluorine, chlorine, bromine, iodine, neon, argon, krypton, xenon or oxygen may be used. The invention may be of utility in highly-integrated SRAM devices which use high resistance polycrystalline silicon as a resistance material.

Verfahren zur herstellung von polykristallinem silizium mit hohem widerstandswert

Procede de fabrication de silicium polycristallin possedant une resistance elevee, comportant : une premiere operation de depot d'une couche de silicium polycristallin pour realiser une surface resistive au-dessus d'un substrat 10 semi-conducteur au silicium; une seconde operation de developpement d'une premiere couche d'oxyde thermique 17 possedant une premiere profondeur specifiee au-dessus de la couche de silicium polycristallin 15, implantation d'ions azote sur celle-ci, et developpement d'une seconde couche d'oxyde thermique 18 possedant une seconde profondeur specifiee sur la couche ayant recu une implantation d'ions; une troisieme operation en vue de realiser un motif de resistance 15' du silicium polycristallin selon un procede de photogravure; et une quatrieme operation d'implantation ionique d'impuretes afin de diminuer la resistance du silicium polycristallin dans des regions de contact 20, 20' destinees a etre utilisees en tant que contacts resistants avec une region semi-conductrice determinee sur le substrat. Application : notamment aux memoires a acces selectif statiques (SRAM).

Jung-Hwan Lee

Papers

Method of making semiconductor devices having ohmic contact

Method of manufacturing high resistance polycrystalline silicon

Verfahren zur herstellung von polykristallinem silizium mit hohem widerstandswert

Procede de fabrication de silicium polycristallin possedant une resistance elevee