Christopher Pulte

TL;DR: This paper develops a concurrency model with a microarchitectural flavour, abstracting from many hardware implementation concerns but still close to hardware-designer intuition, and builds a tool from the combined semantics that lets one explore the full range of architecturally allowed behaviour, for litmus tests and (small) ELF executables.

TL;DR: Two formal concurrency models are defined: an operational one, simplifying the Flowing model of Flur et al., and the axiomatic model of the revised ARMv8 specification, and it is proved the equivalence of the two models.

TL;DR: This paper presents rigorous semantic models for the sequential behaviour of large parts of the mainstream ARMv8-A, RISC-V, and MIPS architectures, and the research CHERI-MIPS architecture, that are complete enough to boot operating systems, variously Linux, FreeBSD, or seL4.

TL;DR: In this article, the authors define two formal concurrency models: an operational one, simplifying the Flowing model of Flur et al., and the axiomatic model of the revised ARMv8 specification.

TL;DR: This paper shows how a precise architectural envelope model for weakly consistent multiprocessor architectures can be defined, taking IBM POWER as an example, and is expressed in a mathematically rigorous language that can be automatically translated to an executable test-oracle tool.