This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14× by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 ? J per feature vector.

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A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System

This paper presents a low-power SoC that performs EEG acquisition and feature extraction required for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital processor that streams features-vectors to a central device where seizure detection is performed via a machine-learning classifier. The instrumentation-amplifier uses chopper-stabilization in a topology that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the ADC employs power-gating for low energy-per-conversion while using static-biasing for comparator precision; the EEG feature extraction processor employs low-power hardware whose parameters are determined through validation via patient data. The integration of sensing and local processing lowers system power by 14x by reducing the rate of wireless EEG data transmission. Feature vectors are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply, consuming 9 μJ per feature vector.

Describes the implementation of a wide dynamic range voiceband switched-capacitor filter using a differential chopper-stabilized configuration. The noise behavior of switched-capacitor filters is discussed qualitatively, and the effects of the chopper stabilization on the noise performance is analyzed. Experimental results from a fifth-order low-pass voiceband prototype are presented.

A low-noise chopper-stabilized differential switched-capacitor filtering technique

The noise response of switched capacitor networks (SCNs) is reviewed with emphasis on simplifying approximations suitable for SPICE noise simulation. The techniques developed cover all op-amp noise sources, as well as capacitor switching noise. The close agreement between predicted and measured noise responses for several monolithic SCNs bears out the validity of these simulation techniques.

Noise sources and calculation techniques for switched capacitor filters

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-/spl mu/m single-poly n-well CMOS process. It features a gain of 52 dB with a 500 Hz bandwidth and a common-mode rejection ratio (CMRR) of more than 70 dB. The equivalent input low frequency noise is 15 nV//spl radic/Hz. The typical residual input offset is 1.5 /spl mu/V. The amplifier power consumption is 1.3 mW.

A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors

It is shown that the noise generated in a passive first-order switched-capacitor lowpass filter has its origin in the thermal noise of the m.o.s. transistors' on-resistance. The spectral description of this noise at the output of the filter is given. The measurements made on a discrete laboratory model show good correspondence with the analytical results and confirm the noise model established.

Cl.-A. Gobet

Papers

Noise generated in switched capacitor networks