An integrated circuit having boundary-scan facilities in accordance with IEEE Standard 1149.1, has its boundary scan chain configured to permit fault insertion testing of diagnostic and maintenance software. Each Scan cell includes storage devices for storing a pair of bits of a binary vector shifted into the boundary scan chain. One bit comprises faulty data and the other bit serves to control application of the faulty data by the scan cell. A system incorporating such integrated circuits includes a controller for controlling the IEEE test interface to shift the binary vector into the boundary scan chain, and diagnostic and maintenance software for diagnosing the faults introduced into the integrated circuits.

Software verification by fault insertion

A system and method for fault injection utilizing boundary scan includes the provision of an additional fault injection register to the standard JTAG architecture in order to allow the intentional introduction of faults into a device or module forming part of a system under test. Through the use of the fault injection register of the present invention, faults may be intentionally introduced and the system response to such faults monitored and analyzed independently of the system software and without the use of mechanical probes or the like for introducing the fault. The system and method of the present invention is readily integrated with the existing test functions of the standard IEEE 1149.1 boundary scan architecture.

Fault injection using boundary scan

A power converter controller is disclosed. An example controller includes a control circuit coupled to receive a feedback signal representative of an output of the power converter. The control circuit coupled to control a switching of a power switch of the power converter in response to the feedback signal to control a transfer of energy from an input of the power converter to the output of the power converter. An internal programming interface circuit is coupled to the control circuit. A coupling switcher is coupled to the internal programming interface circuit. An external programming terminal is selectively coupled to the internal programming interface circuit through the coupling switcher. An external programming circuit coupled to the external programming terminal is coupled to the internal programming interface circuit through the coupling switcher during a startup programming condition and during a fault condition of the power converter. The external programming circuit that is coupled to the external programming terminal is decoupled from the internal programming interface circuit by the coupling switcher during a normal operating condition of the power converter.

Method and apparatus for programming a power converter controller with an external programming terminal having multiple functions

The system and methods described herein relate to testing and verifying the fault tolerance in fault tolerant systems. Fault logic integrated into a fault tolerant system permits automated testing of fault paths in system firmware and hardware dedicated to handling fault scenarios. Advantages of the disclosed system and methods include the ability to inject errors without the need to modify system firmware or hardware. Errors can be injected in a controlled manner and asynchronously to normal system firmware execution which permits improved coverage of firmware error paths. The automated error injection capability disclosed is applicable in both the development and production of fault tolerant systems.

System and methods for fault path testing through automated error injection

A method for testing a circuit board having both boundary-scan and non-boundary-scan devices is provided. The test method distinguishes boundary-scan nodes from non-boundary-scan nodes and uses cartesian coordinates (X,Y) of every pin of every device on the circuit board to determine a number of sets of non-boundary-scan nodes that are within a predetermined distance "R" from a device pin coupled to a boundary-scan node. The number of sets of non-boundary-scan nodes are grouped into "independent" groups which can be tested in parallel. A test cycle is performed by testing independent non-boundary-scan nodes in parallel by forcing drivers in the boundary-scan devices to a first logic state, and forcing each of the non-boundary-scan nodes to another logic state for a brief interval. Receivers on the boundary-scan devices capture a response vector during the brief interval, which is scanned out of the circuit board for evaluation. The response vector reflects which of the nodes has failed, and cartesian coordinate data giving the precise location of any faulty node(s) is returned to user.

Powered testing of mixed conventional/boundary-scan logic

Fault insertion circuits under programmable control and resident in an integrated circuit (LSI or VLSI) (10) insert transient and intermittent fault classes in addition to a permanent fault class into functional logic (24) on such integrated circuit (10). Specific fault types programmable for each fault class include a stuck-open fault and bridging faults both wired-AND and wired-OR. The programmable fault insertion circuitry on each integrated circuit interfaces directly or indirectly with a BIT maintenance controller (12). In addition to verifying test software, a fault tolerant system's error detection and recovery circuits may be verified by fault insertion testing using the transient and intermittent fault insertions. The controller (12) inserts a fault (11) into the integrated circuit (10) with control and initialisation data words and monitors the effect of the fault on the functional logic (24). The fault control and initialisation data words are stored in timers (52, 54, 56), a fault word register (14), and an intermittent fault mode logic (60), and are decoded under the control of the controller (12) and a slaved timing and control generator (17) to load a fault type generator (16) which responds by supplying a fault type signal (FAULTn) to a fault insertion interface (18) which thereupon inserts the required fault into functional logic (24) by appropriate modification of the coupling between an output signal (N) from and and an input signal FSIGNAL(N) to the functional logic (24).

Craig A. Chancellor

Papers

Transient and intermittent fault insertion