The Multiply-Accumulate Unit (MAC) is an integral computational component of all digital signal processing (DSP) architectures and thus has a significant impact on their speed and power dissipation. Due to an extraordinary explosion in the number of battery-powered “Internet of Things” (IoT) devices, the need for reducing the power consumption of DSP architectures has tremendously increased. Approximate computing (AxC) has been proposed as a potential solution for this problem targeting error-resilient applications. In this paper, we present a novel FPGA implementation for input-aware energy-efficient 8-bit approximate MAC (AxMAC) unit that reduces its power consumption by: performing multiplication operation approximately, or approximating the input operands then replacing multiplication by a simple shift operation. We propose an input-aware conditional block to bypass operands multiplication by (1) zero forwarding for zero-value operands, (2) judiciously approximating 43.8% of inputs into power-of-2 values, and (3) replacing the multiplication of power-of-2 operands by a simple shift operation. Experimental results show that these simplification techniques reduce delay, power and energy consumption with an acceptable quality degradation. We evaluate the effectiveness of the proposed AxMAC units on two image processing applications, i.e., image blending and filtering, and a logistic regression classification application. These applications demonstrate a negligible quality loss, with 66.6% energy reduction and 5% area overhead.

Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency

In a VLSI system, the pipeline architecture of high-speed modified Booth multipliers are used. The proposed multiplier circuits are based on the modified Booth algorithm. The pipeline technique which are the most widely used to accelerate the multiplication speed. To implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline registers to be inserted. The proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits. The resultant multiplier circuits show better performance than others. Since the proposed multipliers operate at GHz ranges, they can be used in the systems requiring very high performance.

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A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

The rapid advancements in science and technology has augmented the demand for Digital Signal Processors (DSPs) with high computing performance and real time processing capabilities. Multiply Accumulate (MAC) Unit is one of the most significant blocks which helps a DSP to achieve high performance. The performance of the MAC unit determines the ultimate overall performance of the system. Several MAC unit designs have been developed and implemented so far to achieve better performance parameters. This paper provides an overview of the different designs used in a MAC unit in order to improve its performance.

A survey on the design and performance of various MAC unit architectures

In the most of the Digital Signal Processing (DSP) applications, the fundamental operations usually involve multiplications and accumulations. Multiplication is the arithmetic operation in which a processor requires most of its time as well as hardware resources among all other arithmetic operations like addition and subtraction. To attain a high-performance DSP application for real time signal processing applications, efficient Multiply Accumulate Unit (MAC) is always a mainstay. In the last few years, the main focus of MAC design is to boost its speed. This is because speed and throughput rate are always the crucial parameters of DSP systems. In this paper, a survey is done for different kind of MAC unit with different multipliers and adders where, multipliers are used to create partial products while adders to accumulate these partial products. This study reviews various MAC units designed until now with high speed and low power consumption.

A Survey on Multiply Accumulate Unit

In Digital signal processing, Filter is used almost in all devices. Filters are used to extract the useful part from the input signal and the required part of the signal is reached to the receiver. For linear characteristics devices, FIR filter is used which is nothing but a combination of multiplier and adder. In this paper FIR filter has been designed by using a reconfigurable Booth multiplier and a Carry Look Ahead Adder. Combination of Booth multiplier and Carry Look Ahead adder makes FIR filter faster. RTL synthesis has been done by using Xilinx 14.3 and simulation is done by using Modelsim 6.4a. Proposed MAC unit is efficient in terms of speed and complexity and has achieved maximum frequency as 307.977MHz. We have achieved delay for MAC unit as 3.247ns and power 0.242 watt.

Design of FIR Filter using reconfigurable MAC unit

In recent years, Multiply-Accumulate (MAC) unit is developing for various high performance applications. MAC unit is a fundamental block in the computing devices, especially Digital Signal Processor (DSP). MAC unit performs multiplication and accumulation process. Basic MAC unit consists of multiplier, adder, and accumulator. In the existing MAC unit model, multiplier is designed using modified Radix-2 booth multiplier. In this paper, MAC unit model is designed by incorporating the various multipliers such as Array Multiplier, Ripple Carry Array Multiplier with Row Bypassing Technique, Wallace Tree Multiplier and DADDA Multiplier in the multiplier module and the performance of MAC unit models is analyzed in terms of area, delay and power. The performance analysis of MAC unit models is done by designing the models in Verilog HDL. Then, MAC unit models are simulated and synthesized in Xilinx ISE 13.2 for Virtex-6 family 40nm technology.

Design and performance analysis of Multiply-Accumulate (MAC) unit

Finite Impulse Response (FIR) filters are one of the most widely used fundamental filters in digital signal processing system. The modified FIR filters are derived from FIR digital filter. In this paper, design and performance analysis of Fast FIR Algorithm (FFA) based FIR filter and symmetric convolution based FIR filter structures considering 2-parallel and 3-parallel filters is done These entire filter structures are also designed with Carry save Adder (CSA) and Ripple Carry Adder (RCA) by replacing the existing adder considering the increased input bit length and coefficient length from 4-bits to 8-bits. Then the performance metrics of the above two structures is done by designing using Verilog HDL. Then, they are simulated and synthesized using Xilinx ISE 13.2 for Spartan 3E.

Design and study of modified parallel FIR filter using fast FIR algorithm and symmetric convolution

This paper preferences extraction and ranking functions in mobile search that captures the users' preferences in the form of concepts by mining their click through data. Due to the importance of location information in mobile search, it classifies these concepts into content concepts and location concepts. In addition, users' locations (positioned by GPS) are used to supplement the location concepts. The user preferences are organized in an ontology-based, multi-facet user profile, which are used to adapt a personalized ranking function for rank adaptation of future search results. To characterize the diversity of the concepts associated with a query and their relevance's to the users need, four entropies are introduced to balance the weights between the content and location facets. Based on the client-server model, also present a detailed architecture and design for implementation of preferences extraction and ranking functions in mobile search. In our design, the client collects and stores locally the click through data to protect privacy, whereas heavy tasks such as concept extraction, training and re-ranking are performed at the server. Moreover, here address the privacy issue by restricting the information in the user profile exposed to the server with two privacy parameters. To prototype preferences extraction and ranking functions in mobile search on the Google Android platform.

http://ieeexplore.ieee.org/iel7/7005020/7033740/07033886.pdf

Preferences extraction and ranking functions in mobile search

It is discussed in many studies and demonstrated in many pieces of research that based on certain applications, analog design of filter has several issues including complex design, re-use limitations, and accuracy of generating the output at various frequencies. Therefore, instead of analog filter design, the digital design of the filter is preferred for both Finite and Infinite Impulse Response Filter. This paper demonstrates the design of the digital Finite Impulse Response (FIR) filter designed is demonstrated using Ultra-Scale Field Programming Gate Array (FPGA) having chip XCKU3P. The filter is designed using a coefficient multiplier via Canonic Signed Digit (CSD) Technique. The optimized design of the digital filter is carried out via real-time implementation is performed using Ultra-Scale FPGA. The filter is designed and tested with an ordinary filter at 10 MHz and 10 GHz frequencies. The performance analysis of the system is illustrated using the response rate at the bitstream of 16-bit. In the results, it is demonstrated that for 10 MHz frequency design FIR filter in FPGA the 30% faster response filter is achieved at for 10 GHz, the 15% faster response is achieved at the I/O standard of Low Voltage Complementary Metal Oxide Semiconductor (LVCOMS). The optimization of 30% in terms of the response time of the filter is attained using the proposed work. The proposed improved FIR filter design using Ultra-Scale FPGA helps in increasing design performance to increase the speed of overall response of FIR filter that is lacking in ordinary Filters.

D. Ashok Kumar

Papers

Design and performance analysis of Multiply-Accumulate (MAC) unit

Design and study of modified parallel FIR filter using fast FIR algorithm and symmetric convolution

Preferences extraction and ranking functions in mobile search

Design and Performance Analysis of Improved FIR Filter using Ultra-Scale FPGA