The Multiply-Accumulate Unit (MAC) is an integral computational component of all digital signal processing (DSP) architectures and thus has a significant impact on their speed and power dissipation. Due to an extraordinary explosion in the number of battery-powered “Internet of Things” (IoT) devices, the need for reducing the power consumption of DSP architectures has tremendously increased. Approximate computing (AxC) has been proposed as a potential solution for this problem targeting error-resilient applications. In this paper, we present a novel FPGA implementation for input-aware energy-efficient 8-bit approximate MAC (AxMAC) unit that reduces its power consumption by: performing multiplication operation approximately, or approximating the input operands then replacing multiplication by a simple shift operation. We propose an input-aware conditional block to bypass operands multiplication by (1) zero forwarding for zero-value operands, (2) judiciously approximating 43.8% of inputs into power-of-2 values, and (3) replacing the multiplication of power-of-2 operands by a simple shift operation. Experimental results show that these simplification techniques reduce delay, power and energy consumption with an acceptable quality degradation. We evaluate the effectiveness of the proposed AxMAC units on two image processing applications, i.e., image blending and filtering, and a logistic regression classification application. These applications demonstrate a negligible quality loss, with 66.6% energy reduction and 5% area overhead.

Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency

In a VLSI system, the pipeline architecture of high-speed modified Booth multipliers are used. The proposed multiplier circuits are based on the modified Booth algorithm. The pipeline technique which are the most widely used to accelerate the multiplication speed. To implement the optimally pipelined multipliers, many kinds of experiments have been conducted. The speed of the multipliers is greatly improved by properly deciding the number of pipeline stages and the positions for the pipeline registers to be inserted. The proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits. The resultant multiplier circuits show better performance than others. Since the proposed multipliers operate at GHz ranges, they can be used in the systems requiring very high performance.

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A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

The rapid advancements in science and technology has augmented the demand for Digital Signal Processors (DSPs) with high computing performance and real time processing capabilities. Multiply Accumulate (MAC) Unit is one of the most significant blocks which helps a DSP to achieve high performance. The performance of the MAC unit determines the ultimate overall performance of the system. Several MAC unit designs have been developed and implemented so far to achieve better performance parameters. This paper provides an overview of the different designs used in a MAC unit in order to improve its performance.

A survey on the design and performance of various MAC unit architectures

In the most of the Digital Signal Processing (DSP) applications, the fundamental operations usually involve multiplications and accumulations. Multiplication is the arithmetic operation in which a processor requires most of its time as well as hardware resources among all other arithmetic operations like addition and subtraction. To attain a high-performance DSP application for real time signal processing applications, efficient Multiply Accumulate Unit (MAC) is always a mainstay. In the last few years, the main focus of MAC design is to boost its speed. This is because speed and throughput rate are always the crucial parameters of DSP systems. In this paper, a survey is done for different kind of MAC unit with different multipliers and adders where, multipliers are used to create partial products while adders to accumulate these partial products. This study reviews various MAC units designed until now with high speed and low power consumption.

A Survey on Multiply Accumulate Unit

In Digital signal processing, Filter is used almost in all devices. Filters are used to extract the useful part from the input signal and the required part of the signal is reached to the receiver. For linear characteristics devices, FIR filter is used which is nothing but a combination of multiplier and adder. In this paper FIR filter has been designed by using a reconfigurable Booth multiplier and a Carry Look Ahead Adder. Combination of Booth multiplier and Carry Look Ahead adder makes FIR filter faster. RTL synthesis has been done by using Xilinx 14.3 and simulation is done by using Modelsim 6.4a. Proposed MAC unit is efficient in terms of speed and complexity and has achieved maximum frequency as 307.977MHz. We have achieved delay for MAC unit as 3.247ns and power 0.242 watt.

Design of FIR Filter using reconfigurable MAC unit

In recent years, Multiply-Accumulate (MAC) unit is developing for various high performance applications. MAC unit is a fundamental block in the computing devices, especially Digital Signal Processor (DSP). MAC unit performs multiplication and accumulation process. Basic MAC unit consists of multiplier, adder, and accumulator. In the existing MAC unit model, multiplier is designed using modified Radix-2 booth multiplier. In this paper, MAC unit model is designed by incorporating the various multipliers such as Array Multiplier, Ripple Carry Array Multiplier with Row Bypassing Technique, Wallace Tree Multiplier and DADDA Multiplier in the multiplier module and the performance of MAC unit models is analyzed in terms of area, delay and power. The performance analysis of MAC unit models is done by designing the models in Verilog HDL. Then, MAC unit models are simulated and synthesized in Xilinx ISE 13.2 for Virtex-6 family 40nm technology.

Maroju Sai Kumar

Papers

Design and performance analysis of Multiply-Accumulate (MAC) unit