Proceedings ArticleDOI
Design and performance analysis of Multiply-Accumulate (MAC) unit
Maroju Sai Kumar,D. Ashok Kumar,P. Samundiswary +2 more
- pp 1084-1089
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TLDR
MAC unit model is designed by incorporating the various multipliers such as Array Multiplier, Ripple Carry Array Multipler with Row Bypassing Technique, Wallace Tree Multipliers and DADDA MultiplIER in the multiplier module and the performance of MAC unit models is analyzed in terms of area, delay and power.Abstract:
In recent years, Multiply-Accumulate (MAC) unit is developing for various high performance applications. MAC unit is a fundamental block in the computing devices, especially Digital Signal Processor (DSP). MAC unit performs multiplication and accumulation process. Basic MAC unit consists of multiplier, adder, and accumulator. In the existing MAC unit model, multiplier is designed using modified Radix-2 booth multiplier. In this paper, MAC unit model is designed by incorporating the various multipliers such as Array Multiplier, Ripple Carry Array Multiplier with Row Bypassing Technique, Wallace Tree Multiplier and DADDA Multiplier in the multiplier module and the performance of MAC unit models is analyzed in terms of area, delay and power. The performance analysis of MAC unit models is done by designing the models in Verilog HDL. Then, MAC unit models are simulated and synthesized in Xilinx ISE 13.2 for Virtex-6 family 40nm technology.read more
Citations
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Journal ArticleDOI
Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency
TL;DR: A novel FPGA implementation for input-aware energy-efficient 8-bit approximate MAC (AxMAC) unit that reduces its power consumption by performing multiplication operation approximately, or approximating the input operands then replacing multiplication by a simple shift operation is presented.
Journal ArticleDOI
A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
P.Sasi Bala,S. Raghavendra +1 more
TL;DR: The proposed modified Booth multiplier circuits in Verilog HDL and synthesized the gate-level circuits show better performance than others and can be used in the systems requiring very high performance.
Proceedings ArticleDOI
A survey on the design and performance of various MAC unit architectures
S. Rakesh,K. S. Vijula Grace +1 more
TL;DR: This paper provides an overview of the different designs used in a MAC unit in order to improve its performance.
Proceedings ArticleDOI
A Survey on Multiply Accumulate Unit
TL;DR: A survey is done for different kind of MAC unit with different multipliers and adders where, multipliers are used to create partial products while adders to accumulate these partial products.
Proceedings ArticleDOI
Design of FIR Filter using reconfigurable MAC unit
Deepika,Nidhi Goel +1 more
TL;DR: In this paper FIR filter has been designed by using a reconfigurable Booth multiplier and a Carry Look Ahead Adder to make FIR filter faster.
References
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Journal ArticleDOI
A Reduced Complexity Wallace Multiplier Reduction
TL;DR: A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction, producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.
Journal Article
New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm
Young-Ho Seo,Dong-Wook Kim +1 more
TL;DR: In this article, the authors proposed a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic, by combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved.
Journal ArticleDOI
A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
Young-Ho Seo,Dong-Wook Kim +1 more
TL;DR: The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency.
Proceedings ArticleDOI
Vedic Mathematics Based Multiply Accumulate Unit
TL;DR: The proposed Vedic multiplier used inside the MAC unit is based on the Sutra "Urdhva Tiryagbhyam" (Vertically and Cross wise) which is one of the Sutras of Vedic mathematics which was rediscovered in early twentieth century.
Journal ArticleDOI
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit
TL;DR: This work proposes a high-speed and energy-efficient two-cycle multiply-accumulate (MAC) architecture that supports two's complement numbers, and includes accumulation guard bits and saturation circuitry, and extends the new architecture to create a versatile double-throughput MAC (DTMAC) unit that efficiently performs either multiply- Accumulate or multiply operations for N-bit, 1 × N/2- bit, or 2 × N-2-bit operands.