Logic circuits were designed and fabricated in a 1 µm silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional "Weinberger" layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21- ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed.

1 &#181;m MOSFET VLSI technology: Part III&#8212;Logic circuit design methodology and applications

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.

A 20 ns 64K (4Kx16) NMOS RAM

For pt. II see ibid., vol.SC14, no.2, p.247 (1979). Logic circuits were designed and fabricated in a 1 /spl mu/m silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional `Weinberger' layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration. Second, two forms of PLA and PLA-based macros are discussed. A dynamic PLA, used in a microprocessor cross section and including 105 product terms, which achieves a 56 ns cycle time is described. A static PLA, designed for 21-ns delay and achieving measured delays from 13 to 21 ns, is also described. Extensions, particularly into low-temperature operation, are discussed.

1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications

A push-pull driver circuit wherein the input signals is applied to turn on one of two transistors mounted in series and the inversion of that signal is applied to the second transistor in the series path and the output taken from between them operates to isolate the load and since one and only one of the two transistors in the series path is conducting there is a path to charge and discharge the load capacitance but no path through both devices for power dissipation. The driver circuit can be built into a 2-bit partitioning circuit which in turn, when used with a programmed logic array and the relative capacitance of the various parts being isolated from each other by a coupling circuit, the resulting assembly provides a high performance programmed array logic device.

Logic and array logic driving circuits

A 1μ MOSFET process used for dynamic and static PLAs operating at ns speeds will be discussed. Measurements on 8b ALU test wafers have indicated delays of 13-21ns at 15-24mW.

https://ieeexplore.ieee.org/iel6/8294/25926/01156010.pdf

One micron MOSFET PLAs

A FET logic configuration that uses both enhancement-mode and depletion-mode devices in a single-input, multiple-output logic circuit, will be covered, citing improvement of power-delay product by a factor of four.

http://ieeexplore.ieee.org/iel6/8293/25925/01155813.pdf

D. Conrad

Papers

FET logic configuration