Proceedings ArticleDOI
FET logic configuration
E. Blaser,D. Conrad +1 more
- pp 14-15
TLDR
A FET logic configuration that uses both enhancement-mode and depletion-mode devices in a single-input, multiple-output logic circuit, will be covered, citing improvement of power-delay product by a factor of four.Abstract:
A FET logic configuration that uses both enhancement-mode and depletion-mode devices in a single-input, multiple-output logic circuit, will be covered, citing improvement of power-delay product by a factor of four.read more
Citations
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Journal ArticleDOI
1 µm MOSFET VLSI technology: Part III—Logic circuit design methodology and applications
TL;DR: In this article, conventional random logic chip images using the largely one-dimensional "Weinberger" layout are examined, and the image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of integration.
Journal ArticleDOI
A 20 ns 64K (4Kx16) NMOS RAM
TL;DR: A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns, and an address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.
Journal ArticleDOI
1 /spl mu/m MOSFET VLSI technology. III. Logic circuit design methodology and applications
TL;DR: First, conventional random logic chip images using the largely one-dimensional `Weinberger' layout are examined and two forms of PLA and PLA-based macros are discussed.
Patent
Logic and array logic driving circuits
TL;DR: In this paper, a push-pull driver circuit is proposed to turn on one of two transistors mounted in series and the inversion of that signal is applied to the second transistor in the series path and the output taken from between them operates to isolate the load.
Proceedings ArticleDOI
One micron MOSFET PLAs
TL;DR: In this paper, a 1μ MOSFET process used for dynamic and static PLAs operating at ns speeds was discussed, and it was shown that 8b ALU test wafers have a delay of 13-21ns at 15-24mW.