It is a well-known phenomenon that two solids with sufficiently flat surfaces can stick to each other when brought into intimate contact in ambient air at room temperature. The attraction between the two bodies is primarily mediated through van der Waals forces or hydrogen bonding. Without a subsequent heating step, that type of bonding is reversible. Annealing may increase the energy of adhesion up to the cohesive strength of the materials concerned. The wafer bonding phenomena in brittle materials systems, especially in silicon, is reviewed in the experiment. The focus is on low temperature bonding techniques. The pivotal influence chemical species on the surfaces have on the subsequent type of bonding (van der Waals, hydrogen, covalent bonding, mechanical interlocking) is discussed. Methods of modifying the surface chemistry for tailoring bonding properties are addressed. The paper is aimed at providing an overview of the current understanding of the factors determining the bondability and strength of the bonding obtainable. The authors assess the present state of the experimental methods for determining basic parameters governing the adhesion. A number of examples illustrate the applicability of fusion bonding for as diverse fields as opto-electronics, microsystems technology, and fabrication of advanced substrates like silicon-on-insulator wafers.

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Wafer direct bonding: tailoring adhesion between brittle materials

Strained-semiconductor-on-insulator device structures

A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer

CONTROLLING THREADING DISLOCATION DENSITIES IN Ge ON Si USING GRADED GeSi LAYERS AND PLANARIZATION

A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded SIl-xGex(x increases from 0 to y) is deposited on a first silicone substrate, followed by deposition of a relaxed Sil-yGey layer, a thin strained Sil-zGez layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Sil-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Sil-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Sil-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

Process for producing semiconductor article using graded epitaxial growth

Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.

Hybrid fin field-effect transistor structures and related methods

Fabrication of Bond and Etch‐Back Silicon on Insulator Using a Strained Si0.7Ge0.3 Layer as an Etch Stop

The bond-and-etchback silicon-on-insulator (BESOI) substrates utilize a novel silicon-germanium etch-stop fabrication method to produce a device-film which is thin, defect-free, and highly resistive. Other features of these BESOI substrates include a high-quality thermal oxide at all silicon/insulator interfaces and a buried isolation layer which is fabricated using a radiation-hardened process. Results are presented for CMOS devices and circuits fabricated on these BESOI substrates for which the device-films are 0.25- mu m thick. Test results indicate that circuit performance is improved by more than 30% over the bulk controls and is not adversely affected by incorporating buried layers, and gate and field oxides optimized for radiation environments in the BESOI process. >

http://ieeexplore.ieee.org/iel2/591/4230/00162882.pdf

D. J. Godbey

Papers

Fabrication of Bond and Etch‐Back Silicon on Insulator Using a Strained Si0.7Ge0.3 Layer as an Etch Stop

CMOS on bonded wafers fabricated using a novel Si-Ge etch stop