New carrier mobility data for both arsenic- and boron-doped silicon are presented in the high doping range. The data definitely show that the electron mobility in As-doped silicon is significantly lower than in P-doped silicon for carrier concentrations higher than 1019cm-3. By integrating these data with those previously published, empirical relationships able to model the carrier mobility against carrier concentration in the whole experimental range examined to date (about eight decades in concentration) for As-, P-, and B-doped silicon are derived. Different parameters in the expression for the n-type dopants provide differentiation between the electron mobility in As-and in P-doped silicon. Finally, it is shown that these new expressions, once implemented in the SUPREM II process simulator, lead to reduced errors in the simulation of the sheet resistance values.

Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon

ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESD in Integrated Circuits Effects of Processing and Packaging.

ESD in silicon integrated circuits

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated with the top-level metal of a submicron silicon VLSI process are presented. A computer program which extracts a physics-based model of microstrip components that is suitable for circuit (SPICE) simulation has been used to evaluate the effect of variations in metallization, layout geometry, and substrate parameters upon monolithic inductor performance. Three-dimensional (3-D) numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most very large scale integration (VLSI) technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.

The modeling, characterization, and design of monolithic inductors for silicon RF IC's

Ultra-thin MoS2 has recently emerged as a promising two-dimensional semiconductor for electronic and optoelectronic applications. Here, we report high mobility (>60 cm2/Vs at room temperature) field-effect transistors that employ unencapsulated single-layer MoS2 on oxidized Si wafers with a low level of extrinsic contamination. While charge transport in the sub-threshold regime is consistent with a variable range hopping model, monotonically decreasing field-effect mobility with increasing temperature suggests band-like transport in the linear regime. At temperatures below 100 K, temperature-independent mobility is limited by Coulomb scattering, whereas, at temperatures above 100 K, phonon-limited mobility decreases as a power law with increasing temperature.

Band-like transport in high mobility unencapsulated single-layer MoS 2 transistors

A Caughey–Thomas-like mobility model with temperature and composition dependent coefficients is used in this work to describe the dependence of electron and hole mobilities on temperature, doping concentration, and alloy composition. Appropriate parameter sets are given for a large number of III–V binary and ternary compounds, including: GaAs, InP, InAs, AlAs, GaP, Al0.3Ga0.7As, In0.52Al0.48As, In0.53Ga0.47As, and In0.49Ga0.51P. Additionally, physically justifiable interpolation schemes are suggested to find the mobilities of various ternary and quaternary compounds (such as AlxGa1−xAs, In1−xGaxP, In1−xGaxAs, In1−xAlxAs, and In1−xGaxAsyP1−y) in the entire range of composition. The models are compared with numerous measured Hall data in the literature and very good agreement is observed. The limitations of the present model are also discussed. The results of this work should be extremely useful in device simulation packages, which are currently lacking a reliable mobility model for the above materials.

Empirical low-field mobility model for III-V compounds applicable in device simulation codes

Modelling the bipolar transistor

The frequency performance of AlGaAs/GaAs heterojunction bipolar transistors (HBTs) having different layouts, doping profiles, and layer thicknesses was assessed using the BIPOLE computer program. The optimized design of HBTs was studied, and the high current performances of HBTs and polysilicon emitter transistors were compared. It is shown that no current crowding effect occurs at current densities less than 1*10/sup 5/ A/cm/sup 2/ for the HBT with emitter stripe width S/sub E/ >

Design study of AlGaAs/GaAs HBTs

Analytic expressions representing a double diffused transistor impurity profile are used to calculate the current components in IIL structures The expression for the hole current is given for IIL structures with the epitaxial layer grown on a wide n+substrate and for buried layer structures It was found that an equivalent recombination velocity at the n-n+interface, S_{nn+} , is of order 102higher in buried layer structures than in structures with the epitaxial layer grown on a wide n+substrate for comparable doping levels Results obtained using the analytic expressions are compared with those obtained using a computer program which includes heavy doping effects and doping level mobility dependence Both calculated and computed results are also compared with measured currents for a given IIL structure with the epitaxial layer grown on a wide n+substrate The calculated and the computed results are in good agreement with the experimental results

Vertical current components in integrated injection logic

A bipolar transistor model, compatible with circuit analysis programs, that can model base punchthrough and avalanche breakdown conditions, is presented. The model equations are derived for low to medium current densities and the analytical and experimental methods of obtaining the required parameters are described. Simulation results using the WATAND circuit simulator are compared to experimental measurements for two different bipolar transistors and are shown to agree very well in the normal and inverse modes of operation.

Modeling of narrow-base bipolar transistors including variable-base-charge and avalanche effects

Analytic expressions representing a double-diffused transistor impurity profile are used to calculate the current density and base transit time in a normal transistor and in an inverted (IIL) structure. The calculated current density and transit time for the simplified model and those computed for a double Gaussian impurity profile using the variable boundary regional approach are compared.

D.J. Roulston

Papers

Modelling the bipolar transistor

Design study of AlGaAs/GaAs HBTs

Vertical current components in integrated injection logic

Modeling of narrow-base bipolar transistors including variable-base-charge and avalanche effects

Current and base transit-time relations in normal and inverted (IIL) bipolar transistors