In this paper, design aspects of high-speed digital and analog IC's are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the IC's must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links.

Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s

Fully scalable, analytical HF noise parameter equations for bipolar transistors are presented and experimentally tested on high speed Si and SiGe technologies. A technique for extracting the complete set of transistor noise parameters from Y parameter measurements only is developed and verified. Finally, the usefulness of the noise model is demonstrated in the design of tuned LNAs in the 1.9 GHz, 2.4 GHz, and 5.8 GHz bands.

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A scalable high frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design

This paper presents Si/SiGe:C and InP/GaAsSb HBTs which feature specific assets to address submillimeter-wave and THz applications. Process and modeling status and challenges are reviewed. The specific topics of thermal and substrate effects, reliability, and HF measurements are also discussed.

Si/SiGe:C and InP/GaAsSb Heterojunction Bipolar Transistors for THz Applications

Measuring techniques of the die surface temperature in integrated circuits are reported as very appropriate for failure analysis, for thermal characterization, and for testing modern devices. The paper is arranged as a survey of techniques oriented towards measuring the temperature dynamics of the circuit surface and presenting and discussing both the merits and drawbacks of each technique with regard to the accuracy, reliability and efficiency of the measurements. Two methods are presented in detail: laser probing methods, based on interferometry and thermoreflectance, and embedded CMOS circuit sensors. For these techniques, the physical principles, the state of the art in figures of merit and some application examples are presented

Dynamic Surface Temperature Measurements in ICs

This paper presents for the first time a full three-dimensional (3-D), multilayer, and multichip thermal component model, based on finite differences, with asymmetrical power distributions for dynamic electrothermal simulation. Finite difference methods (FDMs) are used to solve the heat conduction equation in three dimensions. The thermal component model is parameterized in terms of structural and material properties so it can be readily used to develop a library of component models for any available power module. The FDM model is validated with a full analytical Fourier series-based model in two dimensions. Finally, the FDM thermal model is compared against measured data acquired from a newly developed high-speed transient coupling measurement technique. By using the device threshold voltage as a time-dependent temperature-sensitive parameter (TSP), the thermal transient of a single device, along with the thermal coupling effect among nearby devices sharing common direct bond copper (DBC) substrates, can be studied under a variety of pulsed power conditions.

3-D Thermal Component Model for Electrothermal Analysis of Multichip Power Modules With Experimental Validation

A new method is described which allows substrate thermal coupling between active devices to be accurately represented in a circuit simulation environment. The method, based on a substrate thermal equivalent circuit containing resistors and voltage-controlled voltage sources, allows for exact representation of substrate thermal coupling at any number of evaluation points. The topology of the equivalent circuit and derivation of its coefficients is described, and application of the technique to inter- and intradevice thermal effects is illustrated. The method is applied with a simple self-heating compact model representation to a measured GaAs device characteristic exhibiting gain collapse, and is found to accurately predict electrothermal behavior.

Equivalent circuit modeling of static substrate thermal coupling using VCVS representation

A new approach for modelling the dependence of bipolar transistor characteristics on emitter width and length is presented. The new model, verified by device simulation and measurement, predicts device behavior accurately over a wide range of emitter aspect ratios.

Predictive modelling of lateral scaling in bipolar transistors

An R/sub TH/-VCVS equivalent circuit approach is presented which allows thermal coupling to be accurately represented in circuit simulation. The method is applied to a multi-segment GaAs HBT device, and current gain collapse is successfully predicted with physical model parameters.

D.J. Walkey

Papers

Equivalent circuit modeling of static substrate thermal coupling using VCVS representation

Predictive modelling of lateral scaling in bipolar transistors

A VCVS-based equivalent circuit model for static substrate thermal coupling