Showing papers in "IEEE Journal of Solid-state Circuits in 2002"

Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration

Abstract: A model describing the maximum clock frequency (FMAX) distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor. The model agrees closely with measured data in mean, variance, and shape. Results demonstrate that within-die fluctuations primarily impact the FMAX mean and die-to-die fluctuations determine the majority of the FMAX variance. Employing rigorously derived device and circuit models, the impact of die-to-die and within-die parameter fluctuations on future FMAX distributions is forecast for the 180, 130, 100, 70, and 50-nm technology generations. Model predictions reveal that systematic within-die fluctuations impose the largest performance degradation resulting from parameter fluctuations. Assuming a 3/spl sigma/ channel length deviation of 20%, projections for the 50-nm technology generation indicate that essentially a generation of performance gain can be lost due to systematic within-die fluctuations. Key insights from this work elucidate the recommendations that manufacturing process controls be targeted specifically toward sources of systematic within-die fluctuations, and the development of new circuit design methodologies be aimed at suppressing the effect of within-die parameter fluctuations.

Analysis and design of a 1.8-GHz CMOS LC quadrature VCO

Abstract: This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results A prototype for the QVCO was implemented in a 035-/spl mu/m CMOS process with three standard metal layers The QVCO could be tuned between 164 and 197 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply The equivalent phase error between I and Q signals was at most 025/spl deg/

Fully integrated CMOS power amplifier design using the distributed active-transformer architecture

Abstract: A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while maintaining a 50-/spl Omega/ match. It also uses virtual ac grounds and magnetic couplings extensively to eliminate the need for any off-chip component, such as tuned bonding wires or external inductors. Furthermore, it desensitizes the operation of the amplifier to the inductance of bonding wires making the design more reproducible. To demonstrate the feasibility of this concept, a 2.4-GHz 2-W 2-V truly fully integrated power amplifier with 50-/spl Omega/ input and output matching has been fabricated using 0.35-/spl mu/m CMOS transistors. It achieves a power added efficiency (PAE) of 41 % at this power level. It can also produce 450 mW using a 1-V supply. Harmonic suppression is 64 dBc or better. This new topology makes possible a truly fully integrated watt-level gigahertz range low-voltage CMOS power amplifier for the first time.

A sub-1-V 15-ppm//spl deg/C CMOS bandgap voltage reference without requiring low threshold voltage device

Abstract: A sub-1-V CMOS bandgap voltage reference requiring no low threshold voltage device is introduced in this paper. In a CMOS technology with V/sub thn/ /spl ap/ |V/sub thp/| /spl ap/ 0.9 V at 0/spl deg/C, the minimum supply voltage of the proposed voltage reference is 0.98 V, and the maximum supply current is 18 /spl mu/A. A temperature coefficient of 15 ppm//spl deg/C from 0/spl deg/C to 100/spl deg/C is recorded after trimming. The active area of the circuit is about 0.24 mm/sup 2/.

Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters

Abstract: A wireless interconnect system which transmits and receives RF signals across a chip using integrated antennas, receivers, and transmitters is proposed and demonstrated. The transmitter consists of a voltage-controlled oscillator, an output amplifier, and an antenna, while the receiver consists of an antenna, a low-noise amplifier, a frequency divider, and buffers. Using a 0.18-/spl mu/m CMOS technology, each of these individual circuits is demonstrated at 15 GHz. Wireless interconnection for clock distribution is then demonstrated in two stages. First, a wireless transmitter with integrated antenna generates and broadcasts a 15-GHz global clock signal across a 5.6-mm test chip, and this signal is detected using receiving antennas. Second, a wireless clock receiver with an integrated antenna detects a 15-GHz global clock signal supplied to an on-chip transmitting antenna located 5.6 mm away from the receiver, and generates a 1.875-GHz local clock signal. This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with an integrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results.

A noise-shifting differential Colpitts VCO

Abstract: A novel noise-shifting differential Colpitts VCO is presented. It uses current switching to lower phase noise by cyclostationary noise alignment and improve the start-up condition. A design strategy is also devised to enhance the phase noise performance of quadrature coupled oscillators. Two integrated VCOs are presented as design examples.

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion

Abstract: The tuning curve of an LC-tuned voltage-controlled oscillator (VCO) substantially deviates from the ideal curve 1//spl radic/(LC(V)) when a varactor with an abrupt C(V) characteristic is adopted and the full oscillator swing is applied directly across the varactor. The tuning curve becomes strongly dependent on the oscillator bias current. As a result, the practical tuning range is reduced and the upconverted flicker noise of the bias current dominates the 1/f/sup 3/ close-in phase noise, even if the waveform symmetry has been assured. A first-order estimation of the tuning curve for MOS-varactor-tuned VCOs is provided. Based on this result, a simplified phase-noise model for double cross-coupled VCOs is derived. This model can be easily adapted to cover other LC-tuned oscillator topologies. The theoretical analyses are experimentally validated with a 0.25 /spl mu/m CMOS fully integrated VCO for 5 GHz wireless LAN receivers. By eliminating the bias current generator in a second oscillator, the close-in phase noise improves by 10 dB and features -70 dBc/Hz at 10 kHz offset. The 1/f/sup 2/ noise is -132 dBc/Hz at 3 MHz offset. The tuning range spans from 4.6 to 5.7 GHz (21%) and the current consumption is 2.9 mA.

A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysis

Abstract: A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers and other PLL applications in which the divide value is varied in time. Based on the derived model, a general parameterization is presented that further simplifies noise calculations. The framework is used to analyze the noise performance of a custom /spl Sigma/-/spl Delta/ synthesizer implemented in a 0.6 /spl mu/m CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency offset range spanning 25 kHz to 10 MHz.

Single-chip surface micromachined integrated gyroscope with 50/spl deg//h Allan deviation

Abstract: The design principles of a mass-produced surface micromachined gyroscope are described. The device is integrated on a single 3 mm/spl times/3 mm chip with a 3-/spl mu/m BiCMOS process. It has a 4-/spl mu/m-thick polysilicon structure, 5-V 6-mA supply, 12.5-mV//spl deg//S sensitivity, 10 000:1 dynamic range, 30 000-gee shock survival, and -55/spl deg/C to +85/spl deg/C operating temperature.

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

Abstract: A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.

Capacity limits and matching properties of integrated capacitors

Abstract: Theoretical limits for the capacitance density of integrated capacitors with combined lateral and vertical field components are derived. These limits are used to investigate the efficiency of various capacitive structures such as lateral flux and quasifractal capacitors. This study leads to two new capacitor structures with high lateral-field efficiencies. These new capacitors demonstrate larger capacities, superior matching properties, tighter tolerances, and higher self-resonance frequencies than the standard horizontal parallel plate and previously reported lateral-field capacitors, while maintaining comparable quality factors. These superior qualities are verified by simulation and experimental results.

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

Abstract: A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-/spl mu/m CMOS technology, occupies a total active area of 0.05 mm/sup 2/ and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of M=4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72/spl times/72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk).

A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems

Abstract: A 5-GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-compliant WLAN has been integrated in a 0.25-/spl mu/m CMOS technology. The IC has 22-dBm maximum transmitted power, 8-dB overall receive-chain noise figure and -112-dBc/Hz synthesizer phase noise at 1-MHz frequency offset.

A sub-130-nm conditional keeper technique

Abstract: Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction.

The implementation of the Itanium 2 microprocessor

Abstract: This 64-b microprocessor is the second-generation design of the new Itanium architecture, termed explicitly parallel instruction computing (EPIC). The design seeks to extract maximum performance from EPIC by optimizing the memory system and execution resources for a combination of high bandwidth and low latency. This is achieved by tightly coupling microarchitecture choices to innovative circuit designs and the capabilities of the transistors and wires in the 0.18-/spl mu/m bulk Al metal process. The key features of this design are: a short eight-stage pipeline, 11 sustainable issue ports (six integer, four floating point, half-cycle access level-1 caches, 64-GB/s level-2 cache and 3-MB level-3 cache), all integrated on a 421 mm/sup 2/ die. The chip operates at over 1 GHz and is built on significant advances in CMOS circuits and methodologies. After providing an overview of the processor microarchitecture and design, this paper describes a few of these key enabling circuits and design techniques.

Transconductance amplifier structures with very small transconductances: a comparative design approach

Abstract: A family of CMOS operational transconductance amplifiers (OTAs) has been designed for very small G/sub m/'s (of the order of nanoamperes per volt) with transistors operating in moderate inversion. Several OTA design schemes such as conventional, using current division, floating-gate, and bulk-driven techniques are discussed. A detailed comparison has also been made among these schemes in terms of performance characteristics such as power consumption, active silicon area, and signal-to-noise ratio. The transconductance amplifiers have been fabricated in a 1.2-/spl mu/m n-well CMOS process and operate at a power supply of 2.7 V. Chip test results are in good agreement with theoretical results.

A wide-range delay-locked loop with a fixed latency of one clock cycle

Abstract: A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N/spl times/T/sub Dmax/) to 1/(3T/sub Dmin/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 /spl mu/m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz.

A CMOS monolithic /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer for DCS-1800

Abstract: A monolithic 1.8-GHz /spl Delta//spl Sigma/-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-/spl mu/m CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2/spl times/2 mm/sup 2/. To investigate the influence of the /spl Delta//spl Sigma/ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in /spl Delta//spl Sigma/ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints.

Miniature 3-D inductors in standard CMOS process

Abstract: The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-/spl mu/m one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f/sub SR/ of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q/sub max/. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced.

CMOS single-chip gas detection system comprising capacitive, calorimetric and mass-sensitive microsensors

Abstract: A single-chip gas detection system fabricated in industrial CMOS technology combined with post-CMOS micro-machining is presented. The sensors rely on a chemo-sensitive polymer layer, which absorbs predominantly volatile organic compounds (VOCs). A mass-sensitive resonant-beam oscillator, a capacitive sensor incorporated into a second-order /spl Sigma//spl Delta/-modulator, a calorimetric sensor with low-noise signal conditioning circuitry and a temperature sensor are monolithically integrated on a single chip along with all necessary driving and signal conditioning circuitry. The preprocessed sensor signals are converted to the digital domain on chip. An additional integrated controller sets the sensor parameters and transmits the sensor values to an off-chip data recording unit via a standard serial interface. A 6-chip-array has been flip-chip packaged on a ceramic substrate, which forms part of a handheld VOC gas detection unit. Limits of detection (LOD) of 1-5 ppm n-octane, toluene or propan-1-ol have been achieved.

Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator

Abstract: A 5-GHz quadrature LC oscillator has been realized, in which the two LC stages are coupled with phase shifters. Analysis on the behavioral level shows that an N-stage LC oscillator is optimally coupled when each stage is connected with phase shifters providing /spl plusmn/180/spl deg//N phase shift. Simulation of the 5-GHz two-stage quadrature LC oscillator reveals a 4.3-dB reduction in phase noise compared to a quadrature LC oscillator without phase shifters. Measurements of the 5-GHz quadrature LC oscillator, made in a 30-GHz f/sub T/ process, show a phase noise lower than -113 dBc/Hz, with a resonator quality factor of only 4 and an oscillator core power dissipation of 21.2 mW.

Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops

Abstract: This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies [periods of less than 8/spl times/ the delay of a fan-out-4 inverter (FO-4)] and faster frequency acquisition. Prototypes designed in 0.25-/spl mu/m CMOS process exhibit operating frequencies of 1.25 GHz [=1/(8/spl middot/FO-4)] and 1.5 GHz [=1/(6.7/spl middot/FO-4)] for two techniques, respectively, whereas a conventional PFD operates at <1 GHz [=1/(10/spl middot/FO-4)]. The two proposed PFDs achieve a capture range of 1.7/spl times/ and 1.4/spl times/ the conventional design, respectively.

A noise optimization technique for integrated low-noise amplifiers

Abstract: Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near NF/sub min/ by choosing an appropriate device geometry along with an optimal bias condition. An 800 MHz LNA has been implemented in a standard 0.24 /spl mu/m CMOS technology. The amplifier possesses a 0.9 dB noise figure with a 7.1 dBm third-order input intercept point, while drawing 7.5 mW from a 2.0 V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.

A field programmable analog array for CMOS continuous-time OTA-C filter applications

Abstract: A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5/spl times/8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade.

Tail current noise suppression in RF CMOS VCOs

Abstract: This paper presents the experimental results of two different techniques, inductive degeneration and capacitive filtering, for reducing the phase noise in tail-biased RF CMOS voltage-controlled oscillators (VCOs). Both techniques prevent the low-frequency tail current noise from being converted into phase noise. The techniques are applied to two distinct VCO designs, showing that the largest phase noise reduction (up to 6-7 dB at 3-MHz offset frequency from the carrier) is achieved via inductive degeneration. Capacitive filtering, however, also substantially reduces the phase noise at high offset frequencies and may therefore become a valid alternative to inductive degeneration, as discrete capacitors are of more common use than discrete inductors.

Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors

Abstract: A closed-form inductance expression for compact modeling of integrated inductors is presented. The expression is more accurate than previously published closed formulas. Moreover, due to its physics-based nature, it is scalable. That is demonstrated by comparison with the measured inductance for a complete set of inductors with different layout parameters.

An injection-locking scheme for precision quadrature generation

Abstract: We describe a novel quadrature splitter based on injection locking a cascade of ring oscillators to a low-phase-noise (external) single-phase reference clock. The output signals are in accurate quadrature with low phase noise over a wide bandwidth. This scheme inherently operates at high signal frequencies and is insensitive to the shape of the reference clock waveform. Experimental results at 2.7 GHz are reported for a prototype implementation in 0.25-/spl mu/m BiCMOS technology. To prove the viability of this scheme, a single-sideband upconverter was implemented along with the splitter. Over several chips, an average sideband suppression better than 45 dB over a large signal bandwidth of 100 MHz was achieved.

A 0.5-8.5 GHz fully differential CMOS distributed amplifier

Abstract: A fully integrated fully differential distributed amplifier with 5.5 dB pass-band gain and 8.5 GHz unity-gain bandwidth is described. The fully differential CMOS circuit topology yields wider bandwidth than its single-ended counterpart, by eliminating the source degeneration effects of parasitic interconnect, bond wire, and package inductors. A simulated annealing CAD tool underpins the parasitic-aware methodology used to optimize the design including all on-chip active and passive device and off-chip package parasitics. Mixed-mode S-parameter measurement techniques used for fully differential circuit testing are reviewed. Integrated in 1.3/spl times/2.2 mm/sup 2/ in a standard 0.6 /spl mu/m CMOS process, the distributed amplifier dissipates 216 mW from a single 3 V supply.

Equalization and FEC techniques for optical transceivers

Abstract: In this tutorial paper, we present the application of well-known DSP techniques used in lower speed wireline and wireless applications, to high-speed optical communications. After an introduction on today's optical network architecture and typical optical channel impairments, we study techniques such as fiber equalization, maximum likelihood detection, and current and next generations Forward Error Correction (FEC), with special emphasis on VLSI implementation.

An easy-to-use mismatch model for the MOS transistor

Abstract: In this paper, a physics-based mismatch model is presented. It is demonstrated on a 0.18-/spl mu/m technology that a simple mismatch model can still be used to characterize deep-submicron technologies. The accuracy of the model is examined and found to be within 20% in the strong inversion region. Bulk bias dependence is modeled in a physical way. To extract the mismatch parameters, a weighted fit is introduced. It is shown that the width and length dependence of the mismatch parameters is given by the Pelgrom model.