Rapid developments in the field of cryptography and hardware security have increased the need for random number generators which are not only of low-complexity but are also secure to the point of being undeterminable A random number generator is a part of most security systems, so it should be simple and area efficient Many modern-day pseudorandom number generators (PRNGs) make use of linear feedback shift registers (LFSRs) Though these PRNGs are of low complexity, they fall short when it comes to being secure since they are not truly random in nature Thus, in this chapter we propose a random seeding LFSR-based truly random number generator (TRNG) which is not only of low complexity, like the aforementioned PRNGs, but is also ‘truly random’ in nature Our proposed design generates an n-bit truly random number sequence that can be used for a variety of hardware security based applications Based on our proposed n-bit TRNG design, we illustrate an example which generates 16-bit truly random sequences, and a detailed analysis is shown based on National Institute of Standards and Technology (NIST) tests to highlight its randomness

Random seeding LFSR-based TRNG for hardware security applications

Linear Congruential Generator is the popular and most used algorithm for generating the pseudorandom number. The “Modified dual-CLCG” method, said to be secure pseudorandom bit sequence(PRBG) among the various available LFSR, LCG, Dual CLCG that generates a pseudorandom bit sequence at a periodic interval. It depends on the inequality equations to generate a pseudorandom bit sequence at a regular clock cycle with minimum hardware. This method has been developed using different parallel prefix adder based Modified dual CLCG, and the comparison is done for area and delay. This proposed method has been implemented successfully using Verilog-HDL with means of Xilinx ISE (14.7) design suite. For the physical implementation results of Linear Congruential Generator have been done using Spartan 3E. This method is mainly used in the domain of hardware security and also IOT enabled devices.

Implementation of modified Dual-CLCG Method for Pseudorandom bit Generation

Integrated circuits (ICs) are now built and developed in various environments susceptible to changes in malicious design. The worldwide design flow makes it easy for an opponent to pirate IC and manipulates functionality according to the requirements. The main challenge for a designer is to hide the functionality of an IC while passing through another unreliable environment of the design flow. To overcome the scenario, this work proposes a technique of obfuscation known as LUT-based dynamic obfuscation to prevent any malicious modification of the design. In this paper, the obfuscated signals change over time and the design is unpredictable by adding different coding schemes. The minimum cycles required to obtain the correct key bit are 17 cycles for a smaller circuit with six key bit and security in terms of hamming distance is improved to 15% by the optimal selection of the control signal.

Reconfigurable LUT-Based Dynamic Obfuscation for Hardware Security

In the present scenario, the major threat faced by electronic system designers is protecting the device or a circuit from the attackers and Hardware Trojans. Though there is a drastic advancement in the field of cryptography, attackers are finding out the alternative ways of attacking the device. One possible solution of protecting the device is through the usage of random numbers. The true random number generator (TRNG) is used for the generation of random sequence which does not follow any particular pattern or sequence which is a major advantage over pseudo-random number generators (PRNGs). Though the usage of TRNG is highly secure, there are other methods like reverse engineering which may be used by an attacker to break into device. In order to avoid such attacks, this paper proposes the PUF-based design which acts as an irreversible function and is included in the TRNG module. The paper mainly focuses on LFSR-based random seeding which makes the design truly random and produces an unpredictable sequence. An additional level of security to the device is provided by adding PUF. This work provides an irreversible function which is hardly possible to re-engineer, and it provides a completely random sequence, which is evident from the NIST test results.

Power Efficient PUF-Based Random Reseeding True Random Number Generator

UVM based verification of iAPX 186 processor modules

In today's world, as the demand for IC production grows exponentially, testing and validation of all the manufactured chips becomes impossible Therefore, in the proposed method, we have developed a technique for embedding unique signatures with minimalistic hardware or area overhead while preserving the intended functionality To achieve this, three ‘levels’ of security are provided First, circuit specific information is derived and used for signature generation Second, the generated signature is hashed, obfuscating the logic reverse engineering process and finally a bit sequence from a Pseudo-Random Number Generator (PRNG) to make it unfeasibly difficult for the attacker to decode the signature

D Manoj Reddy

Papers

BHARKS: Built-in hardware authentication using random key sequence