Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

A literature survey of the robotic technologies during the COVID-19 pandemic.

A comprehensive review on the problem of choosing a suitable activation function for the hidden layer of a feed forward neural network has been widely investigated. Since the nonlinear component of a neural network is the main contributor to the network mapping capabilities, the different choices that may lead to enhanced performances, in terms of training, generalization, or computational costs, are analyzed, both in general-purpose and in embedded computing environments. Finally, a strategy to convert a network configuration between different activation functions without altering the network mapping capabilities will be presented.

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On training efficiency and computational costs of a feed forward neural network: a review

In this paper, we present an efficient design of lookup-table (LUT) for the evaluation of hyperbolic tangent sigmoid to be used for the hardware implementation of artificial neural networks. Besides, we have suggested an LUT optimization scheme which maximizes the number of argument values in a sub-domain corresponding to each LUT word for a specified limit of accuracy. We have shown that the hardware-complexity of the proposed LUT implementation could be significantly reduced by using simplified combinational circuits for selective sign-conversion and efficient design of range decoder by logic subexpression sharing. From the synthesis results, we find that the proposed design involves comparable delay, but requires less than one-fourth of the area and area-delay complexity compared with the existing LUT-based implementations.

An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks

Globalization of Integrated Circuits (IC's) in semiconductor industries has made them vulnerable to intentional alterations of the design. These intentional alterations to a design are called Hardware Trojans (HT's). Since many of the designs are outsourced for its fabrication, there is a lot of chance for altering its functionality. It is very important to detect these Trojans as it may raise serious concern about hardware trust, especially in the field of military and security applications. This paper considers the detection of combinational trojans using Gate Level Characterization (GLC) and is based on the measurement of side-channel parameters, especially leakage power. The leakage power for an entire circuit is being calculated for each input vector. The obtained measurements are formulated as linear equations in Linear Programming (LP) and are solved using LP solver.

Malicious combinational Hardware Trojan detection by Gate Level Characterization in 90nm technology

Implementation of artificial neural network (ANN) in hardware is needed to fully utilize the inherent parallelism. Presented work focuses on the configuration of field-programmable gate array (FPGA) to realize the activation function utilized in ANN. The computation of a nonlinear activation function (AF) is one of the factors that constraint the area or the computation time. The most popular AF is the log-sigmoid function, which has different possibilities of realizing in digital hardware. Equation approximation, lookup table (LUT) based approach and piecewise linear approximation (PWL) are a few to mention. A two-fold approach to optimize the resource requirement is presented here. Primarily, fixed-point computation (FXP) that needs minimal hardware, as against floating-point computation (FLP) is followed. Secondly, the PWL approximation of AF with more precision is proved to consume lesser Si area when compared to LUT based AF. Experimental results are presented for computation.

FPGA Realization of Activation Function for Artificial Neural Networks

In today's world, as the demand for IC production grows exponentially, testing and validation of all the manufactured chips becomes impossible Therefore, in the proposed method, we have developed a technique for embedding unique signatures with minimalistic hardware or area overhead while preserving the intended functionality To achieve this, three ‘levels’ of security are provided First, circuit specific information is derived and used for signature generation Second, the generated signature is hashed, obfuscating the logic reverse engineering process and finally a bit sequence from a Pseudo-Random Number Generator (PRNG) to make it unfeasibly difficult for the attacker to decode the signature

BHARKS: Built-in hardware authentication using random key sequence

Digital random number generators play a vital role in cryptography applications which is commonly implemented using Linear Feedback Shift Registers (LFSRs). One of the major disadvantages of the LFSR based Random Number Generator (RNG) is that they are easily predictable since the sequences produced are periodic. Therefore, an RNG model is proposed in this paper to increase the unpredictability of the LFSR based RNG by including a polynomial modulator which consists of a multiplexer, a counter and a comparator to select different primitive polynomials. The randomness of the proposed RNG models with varying bit lengths are verified using NIST 800–22 Test suite and their power consumptions are obtained. From the NIS T results, it is evident that the sequences generated by the proposed RNG are random and from the results, it can be inferred that with an increase in the number of bits the power consumption increases.

Design and Synthesis of LFSR based Random Number Generator

Internet of Things (IoT) is considered as the fourth industrial revolution. From small wearables to smart cities, IoT now forms an integral part of society. IoT has also affected the field of Robotics. The Surveillance Robot is based on such a combination of IoT and Robotics. The movement of the robot is remotely controlled by the user. The robot moves according to user instructions and transmits live video footage. Raspberry Pi microcontroller is used to control the robot action. The purpose of the robot is to move around in an area and transmit live video information which the users can see on the user screen. Thus the action of surveillance is done. The surveillance robot has various applications in the field of defense, healthcare, apartment security, etc. This paper proposed an economic, low maintenance, and easy to deploy surveillance robot.

N. Mohankumar

Papers

FPGA Realization of Activation Function for Artificial Neural Networks

Malicious combinational Hardware Trojan detection by Gate Level Characterization in 90nm technology

BHARKS: Built-in hardware authentication using random key sequence

Design and Synthesis of LFSR based Random Number Generator

Security Surveillance Bot for Remote Observation During Pandemics