This paper presents quantitative techniques for the evaluation and comparison of pipelined digital systems. They are based on three measures of effectiveness: delay, average time/operation, and average cost/operation. Moreover, the techniques do not assume that there is an unbounded stream of operations to be performed, although this case is considered. The use of the analysis methods to compare different ways of pipelining a given algorithm is illustrated by an investigation of the pipelining of general four-neighbor cellular arrays. The methods can also be used to evaluate different algorithms for performing the same operation. This is illustrated by comparing three array algorithns for integer multiplication.

Effective Pipelining of Digital Systems

A new algorithm for the multiplication of two n-bit numbers based on the synchronous computation of the partial sums of the two operands is presented. The proposed algorithm permits an efficient realization of the parallel multiplication using iterative arrays. At the same time, it permits high-speed operation. Multiplier arrays for positive numbers and numbers in two's complement form based on the proposed technique are implemented. Also, an efficient pipeline form of the proposed multiplication scheme is introduced. All multipliers obtained have low circuit complexity permitting high-speed operation and the interconnections of the cells are regular, well-suited for VLSI realization.

Multiplexer-based array multipliers

A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Initially, attention is focused on a circuit which is used to multiply streams of parallel unsigned data. We then give details of an algorithm which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features which make it extremely attractive to LSI and VLSI. These include regularity and modularity.

Completely iterative, pipelined multiplier array suitable for VLSI

This paper is concerned with the problem of realizing an arbitrary syndconous or asynchronous sequential machine using only monotone AMR (or decreasing) switching functions. It has been found that h ion always exist, that in the asynchronous case only nomal fundamental mode flow tables are considered. Univesl state assignmments resulting in monotone inceasing (or next-state funtions are characterized using the concept of an (i,j) completely separating system.

Monotone Functions in Sequential Circuits

Observations are made on the effect of pipelining iterative arrays for multiplication. It is suggested that the best type of latched array for multiplication is the save-carry iterative array. The effect of pipelining on other iterative arrays, including the general multiply/divide array is discussed.

Pipeline Iterative Arithmetic Arrays

An iterative array is proposed which reduces the multiplication of two binary numbers to one pass through the array and a summation of the outputs produced.

High-speed iterative multiplier

A systematic procedure for deriving single-transition-time (s.t.t.) state assignments yielding maximum-speed as chronous machines is described. The delay between applying an input and achieving a stable state is two gate delays for all cases.

D.P. Burton

Papers

High-speed iterative multiplier

Maximum-speed s.t.t. state assignments for sequential machines