100-Gb/s dense wavelength division multiplexed (DWDM) transmitter and receiver photonic integrated circuits (PICs) are demonstrated. The transmitter is realized through the integration of over 50 discrete functions onto a single monolithic InP chip. The resultant DWDM PICs are capable of simultaneously transmitting and receiving ten wavelengths at 10 Gb/s on a DWDM wavelength grid. Optical system performance results across a representative DWDM long-haul link are presented for a next-generation optical transport system using these large-scale PICs. The large-scale PIC enables significant reductions in cost, packaging complexity, size, fiber coupling, and power consumption.

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Large-scale photonic integrated circuits

We present an overview of Infinera's current generation of 100 Gb/s transmitter and receiver PICs as well as results from the next-generation 500 Gb/s PM-QPSK PICs.

Optical interconnects are becoming ubiquitous for short-range communication within boards and racks due to higher communication bandwidth at lower power dissipation when compared to metallic interconnects. Efficient multiplexing techniques (wavelengths, time, and space) allow bandwidths to scale; static or predetermined resource allocation of wavelengths can be detrimental to network performance for nonuniform (adversial) workloads. Dynamic bandwidth reallocation (DBR) based on actual traffic pattern can lead to improved network performance by utilizing idle resources. While DBR techniques can alleviate interconnection bottlenecks, power consumption also increases considerably with increase in bit rate and channels. In this paper, we propose to improve the performance of optical interconnects using DBR techniques and simultaneously optimize the power consumption using dynamic power management (DPM) techniques. DBR reallocates idle channels to busy channels (wavelengths) for improving throughput, and DPM regulates the bit rates and supply voltages for the individual channels. A reconfigurable optoelectronic architecture and a performance adaptive algorithm for implementing DBR and DPM are proposed in this paper. Our proposed reconfiguration algorithm achieves a significant reduction in power consumption and considerable improvement in throughput, with a marginal increase in latency for synthetic and real (Splash-2) traffic traces.

Energy-Efficient and Bandwidth-Reconfigurable Photonic Networks for High-Performance Computing (HPC) Systems

We studied the impact of the lithography mask discretization on silicon arrayed waveguide grating (AWG) performance. When we decreased the mask grid from 5 to 1 nm, we observed an experimental improvement in crosstalk of 2.7-6 dB and cumulative crosstalk improvement of 1.2-5 dB, depending on the wavelength channel spacing and the number of output channels. We demonstrate the effect for the AWGs with 200- and 400-GHz channel spacing, with 4, 8, and 16 output wavelength channels. With 1-nm mask grid, the average crosstalk is -26 and -23 dB for 400- and 200-GHz devices, respectively. This is the lowest crosstalk for silicon AWGs reported to the best of our knowledge. A simulation study is performed by looking specifically at phase errors due to mask grid snapping (ignoring other phase error sources), which shows an expected improvement in crosstalk of 12 dB.

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Effect of Mask Discretization on Performance of Silicon Arrayed Waveguide Gratings

The paper proposes a highly connected optical interconnect based architecture that maximizes the channel availability for future scalable parallel computers, such as distributed shared memory (DSM) multiprocessors and cluster networks. As the system size increases, various messages (requests, responses and acknowledgments) increase in the network resulting in contention. This results in increasing the remote memory access latency and significantly affects the performance of these parallel computers. As a solution, we propose an architecture called RAPID (reconfigurable and scalable all-photonic interconnect for distributed-shared memory), that provides low remote memory access latency by providing fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed WDM, TDM and SDM techniques. We evaluated RAPID based on network characteristics and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh and hypercube networks. We found that RAPID outperforms all networks and satisfies most of the requirements of parallel computer design such as low latency, high bandwidth, high connectivity, and easy scalability.

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Design of a high-speed optical interconnect for scalable shared memory multiprocessors

The crosstalk performance of an arrayed-waveguide grating (AWG) multiplexer or demultiplexer is primarily caused by random optical phase errors introduced in the arrayed waveguides. Because the layout of waveguides on a wafer is patterned via photomask through the photolithography process, the resolution of a photomask has a direct influence on the phase errors of an AWG. The paper presents a theoretical analysis on the phase error caused by photomask resolution and other basic design parameters. Both calculation and measurement results show that a high-resolution photomask (better than 25 nm) is a critical requirement to produce low-crosstalk (less than -30 dB) AWG demultiplexers. We also investigate the effect of nonideal power distribution in the arrayed waveguides because it contributes considerable phase errors when material impurity is not well controlled during wafer fabrication. Basic criteria of power profile truncation, number of grating waveguides, and material index variation are also summarized.

The role of photomask resolution on the performance of arrayed-waveguide grating devices

This paper describes a hierarchical WDM-based optical network testbed project that is being constructed to interconnect a large number of high performance computers to create a distributed shared memory environment. The objective of the architecture is to achieve scalability yet avoid the requirement of multiple wavelength tunable devices per node. It is a singlehop all-optical network; a packet remains in the optical form from source to destination. It features wavelength channel reuse at each level, allowing scalability to very large system sizes. It partitions the traffic between different levels of the hierarchy without electronic intervention in a combination of wavelength-division and space-division multiplexing. A significant advantage of this approach is its ability to vary dynamically the bandwidth provided to different levels of the hierarchy. Each node monitors the traffic intensities on each channel and can detect any temporal or spatial shift in traffic balance. LIGHTNING can dynamically reconfigure to balance the traffic at each level by reassigning wavelengths associated with each level in the hierarchy to a higher or lower level depending on need. Bandwidth reallocation is completely decentralized, achieving highly fault tolerant system behavior. This paper describes the system architecture, and the network and memory interface that have been developed in this project.

D. Stone

Papers

The role of photomask resolution on the performance of arrayed-waveguide grating devices

LIGHTNING network and systems architecture