In this paper we present a new data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by Lee [1] and Akers [2], but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a graph of size exponential in the number of arguments, many of the functions encountered in typical applications have a more reasonable representation. Our algorithms have time complexity proportional to the sizes of the graphs being operated on, and hence are quite efficient as long as the graphs do not grow too large. We present experimental results from applying these algorithms to problems in logic design verification that demonstrate the practicality of our approach.

/pdf/graph-based-algorithms-for-boolean-function-manipulation-2u3osq5jc0.pdf

Graph-Based Algorithms for Boolean Function Manipulation

Very high-speed computers may be classified as follows: 1) Single Instruction Stream-Single Data Stream (SISD) 2) Single Instruction Stream-Multiple Data Stream (SIMD) 3) Multiple Instruction Stream-Single Data Stream (MISD) 4) Multiple Instruction Stream-Multiple Data Stream (MIMD). "Stream," as used here, refers to the sequence of data or instructions as seen by the machine during the execution of a program. The constituents of a system: storage, execution, and instruction handling (branching) are discussed with regard to recent developments and/or systems limitations. The constituents are discussed in terms of concurrent SISD systems (CDC 6600 series and, in particular, IBM Model 90 series), since multiple stream organizations usually do not require any more elaborate components. Representative organizations are selected from each class and the arrangement of the constituents is shown.

Very high-speed computing systems

A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digit redundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2 n. The computation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2. It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2 log2 n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

The problem of performing multtphcaUon of n-bit binary numbers on a chip is considered Let A denote the ch~p area and T the time reqmred to perform mult~phcation. By using a model of computation which is a realistic approx~mauon to current and anucipated LSI or VLSI technology, ~t is shown that A T 2.

/pdf/the-area-time-complexity-of-binary-multiplication-4wzuj0r4vl.pdf

The Area-Time Complexity of Binary Multiplication

Until now the use of high radices to implement modular multiplication has been questioned, because it involves complex determination of quotient digits for the module reduction. This paper presents algorithms that are obtained through rewriting of Montgomery's algorithm. The determination of quotients becomes trivial and the cycle time becomes independent of the choice of radix. It is discussed how the critical path in the loop can be reduced to a single shift-and-add operation. This implies that a true speed up is achieved by choosing higher radices. >

Simplifying quotient determination in high-radix modular multiplication

will be less than Cnt+1(t+1)! but may be space into which the latter may be divided multiplier into twenty 2-bit segments. He (and usually will be) more than (t+2)!. by a maximum possible number of mutual then develops an adder tree to sum this set When t= 1 the maximum number of regions intersections of n t-flats. In general, q will be of twenty entries. He then shows that a tree will be dependent on both t and n. It is first shown of nineteen adders (I believe twenty are

A Suggestion for a Fast Multiplier

A procedure is presented for performing a combinatoric fixed-integer division that satisfies the division algorithm in regard to both quotient and remainder. In this procedure, division is performed by multiplying the dividend by the reciprocal of the divisor. The reciprocal is, in all nontrivial cases, of necessity a repeating binary fraction, and two treatments for finding the product of an integer and repeating binary fraction are developed. Two examples of the application of the procedure are given.

A Combinatoric Division Algorithm for Fixed-Integer Divisors

A method for developing combinatoric structures for performing divisions by fixed integers has been demonstrated. In the examples shown the divisions were performed through the use of full adders only, thus illustrating that this technique can be implemented using standard off-the-shelf MSI components.

David H. Jacobsohn

Papers

A Suggestion for a Fast Multiplier

A Combinatoric Division Algorithm for Fixed-Integer Divisors

A combinatoric division algorithm for fixed integer divisors

A Self-Organizing Drum