A 12 bit 160 MS/s two-step pipelined SAR ADC was fabricated in a 40 nm CMOS low-leakage digital process. A background bit-weight calibration exploiting the comparator resolving time information and the employment of a sub-binary DAC in the first SAR stage are two key techniques in this work to attain high conversion throughput and power savings at the same time using a simple, low-gain ( $\sim$ 30 dB) residue amplifier. The overall architecture and the digital calibration also enable the downsizing of the first SAR stage to that of the kT/C limit, yielding a wideband input network delivering an over 80 dB spurious-free dynamic range (SFDR) while digitizing a 300 MHz input at 160 MS/s. The core ADC consumes 4.96 mW and occupies an area of 0.042 mm $^{2}$ ; the calibration circuits dissipate 0.1 mW (estimated). An 86.9 dB SFDR and a 66.7 dB signal-to-noise plus distortion ratio (SNDR) were measured with a 2 V $_{\rm pp}$ , 5 MHz sine-wave input at full speed. The ADC achieves a Walden figure-of-merit (FoM) of 20.7 fJ/conversion-step with a Nyquist input.

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector

We describe a 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling (dynamic), kick-back and memory errors. A new technique is employed to inject a large dither signal on the input to dither the non-linear kick-back on the ADC driver, and another large dither signal is injected to dither any residual non-linearity in the pipeline. In order to correct the effect of aging on the comparators, a new background calibration technique is employed to correct the comparator offsets. The ADC is fabricated as a dual in a 28nm CMOS process. An optional interleaved mode is provided, where the two ADCs on chip are time-interleaved to obtain a single 14-bit 5GS/s ADC. Background calibration of offset and gain mismatch and fixed calibration of timing mismatch between the two channels are implemented on chip.

A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither

This paper presents an energy-efficient 13-bit 10–50 MS/s subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) with power supply scaling. In the presented ADC, an SAR-assisted subranging floating capacitive DAC switching algorithm reduces switching energy along with enhanced linearity and speed in the first-stage SAR ADC. A following temperature-insensitive time-based residue amplifier realizes open-loop residual amplification without background calibration, while maintaining the benefits of dynamic operation and noise filtering. Furthermore, asynchronous SAR control logic employs a pre-window technique to accelerate SAR logic operations. The prototype ADC was fabricated in a 130-nm CMOS process with an active area of 0.22 mm2. With a 1.2-V power supply and a Nyquist frequency input, the ADC consumes 1.32 mW at 50 MS/s and achieves signal-to-noise and distortion ratio and spurious-free dynamic range of 69.1 and 80.7 dB, respectively. The operating speed is scalable from 10 to 50 MS/s with a scalable power supply range of 0.8–1.2 V. Walden FoMs of 4–11.3 fJ/conversion-step are achieved.

A 0.8–1.2 V 10–50 MS/s 13-bit Subranging Pipelined-SAR ADC Using a Temperature-Insensitive Time-Based Amplifier

This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a high-speed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

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A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Each object (such as for example an integrated circuit) of a population of similar objects is configured to generate instances of a dynamic binary identification code (ID) that differ from instances of IDs generated by all other member objects of the population. While bits residing in most of the bit positions of the ID generated by each member object of the population do not vary in state from instance-to-instance of that ID, bits residing in one or more of the bit positions of the ID may vary (drift) in state from instance-to-instance of that ID. A set of instances of the ID generated by each member object of the population are analyzed to construct a separate “drift profile” for each member object's ID indicating for each bit position a probability that the bit position will contain a bit of a particular state. Thereafter, to verify that a particular object is a specific member object of the population, a set of instances of the ID generated by that particular object is analyzed to construct a drift profile for that particular object's ID. That drift profile is then compared to the drift profiles of the IDs generated by the member objects of the population to determine whether the particular object is a certain specific member object of the population.

Method of authenticating an object or entity using a random binary ID code subject to bit drift

We describe a 14-bit 1GS/s pipelined ADC that relies on correlation-based background calibration to correct the inter-stage gain, settling (dynamic) and memory errors. An effective dithering technique is embedded in the calibration signal to break the dependence of the calibration on the input signal amplitude. In addition, to improve the sampling linearity, the ADC employs input distortion cancellation and another digital calibration to compensate for the non-linear charge injection (kickback) from the sampling capacitors on the input driver. The ADC is fabricated in a 65nm CMOS process and has an integrated input buffer. With a 140MHz and 2Vpp input signal, the SNR is 69dB, the SFDR is 86dB, and the power is 1.2W.

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

A high speed transmission system includes at least one transmitter (10d), a buffer circuit (50) for assembling into a data packet in parallel a number of sample conversion words from said transmitter, a marker circuit for adding a marker word (48) to said data packet for framing said data packet, and a serializer (54) circuit for serializing said data packet either before or after said marker word is added, with an embedded clock for transmission.

High speed transmission system

An integrated circuit including a number of repetitive cells for producing output signals in response to respective inputs, each cell(14,16,18) having associated with it an output circuit responsive to the cell output signal to produce an output circuit output signal, each of the output circuits including a circuit device having two terminals to provide for the flow therethrough of a current from an associated current supply(137) and producing a corresponding output signal; the improvement for producing the effectsof cell mismatch and output circuit mismatch including an impedance network(150), having a set of impedance elements each connected between corresponding terminals or respective pairs of the circuits with each circuit device forming a part of a respective output circuit(110,112), the impedance elements reducing the efforts of cell mismatch and output circuit mismatch on the output signals; there maybe one impedance network which accommodates mismatch es in both the cell and output circuits or there may be one impedance network to accommodate cell mismatch and another to accommodate output circuit mismatch.

David Jarman

Papers

29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration

High speed transmission system

Modified repetitive cell matching technique for integrated circuits