Scott Puckett

TL;DR: A 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process with an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art.

TL;DR: A 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET process achieves 80% higher sample rate and 2.4 $\times $ higher input bandwidth, and incorporates a THA that supports a 3.3 non-interleaved sample rate.

TL;DR: A 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling, kick-back and memory errors, fabricated as a dual in a 28nm CMOS process.

TL;DR: This work describes a 16b ADC with a sample rate up to 250MS/s that employs background calibration of the residue amplifier (RA) gain errors to enable wider cellular coverage, more carriers, and to simplify the system design.

TL;DR: In this article, a multi-purpose TV tuner front-end implemented in 0.35/spl mu/m BiCMOS technology is presented, which employs a dual-conversion topology and a fully integrated RF automatic gain control loop.