A method using a generate-and-verify computer program product to generate by repetitive passes a design rules checking computer program, wherein the design rules are described in a file called a runset. The design rules checking program is used for exhaustive testing of VLSI chips for compliance to the design rules of a given VLSI fabrication process. The runset is repeatedly iterated in loop fashion with respect to a testcase file containing groups of layout structures or shapes used for verifying the correctness of the runset. A general purpose shapes processing program creates an error shapes file for storing geometrical errors found in each said layout structure. Two additional shapes are used in the verification process: user boundary shapes for defining areas in which errors are not to be detected for a given design rule, and automated boundary shapes created to surround each said layout structure with a boundary that defines regions where error shapes can occur. An association table is created which is a compilation of the error shapes, user boundary shapes, and automated boundary shapes associated with each layout structure. The association table is processed to determine the correctness of the runset. The runset is modified to correct each valid error. The repetitive passes continue until a final runset is generated. This final runset becomes the input to design rules checking computer program product and customizes the program for a given VLSI fabrication process.

Method for verifying design rule checking software

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Electronic devices and systems, and methods for making and using the same

Integrated circuit chip design in which a technology-independent description of an integrated circuit design is obtained. A first component is selected from a pre-defined first library based on the technology-independent description, and an interconnection is specified between the first component and a second component based on the technology-independent description. The first component and the second component are laid out on a surface of the integrated circuit chip so as to obtain an initial layout, and a routing characteristic for the interconnection is estimated based on the initial layout. The first component is then replaced with a new component selected from a pre-defined second library based on the routing characteristic. According to this aspect of the invention, the pre-defined first library is smaller than the pre-defined second library.

Integrated circuit design with delayed cell selection

A combined heuristic and mathematical programming approach to transistor sizing is presented. A fast heuristic algorithm is used to obtain an initial sizing of the circuit and convert the transistor sizing problem into a nonlinear optimization problem. The problem is then solved, in spaces of reduced dimensionality, by mathematical programming techniques. To cope with the nondifferentiability of the circuit delays, the concept of generalized gradients is proposed to compute the delay sensitivities. Experiments justify the use of this sensitivity computation technique and show that the approach is a good compromise between the speed of the heuristic algorithm and the power of mathematical programming. >

Optimization-based transistor sizing

A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

Programmable structured arrays

Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. This generic CBA library represents several libraries for different process technologies. The resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies. Hence, only one design need be created and simulated. Generic design rule and parasitic parameters are then used to optimize the placement and routing of the generic design. The post-layout generic design is then simulated and verified using performance characteristics determined by a combination of the technologies. The accepted, generic post-layout design is then ported for each intended fabrication process to create the mask patterns associated with each fabrication process.

CAD and simulation system for targeting IC designs to multiple fabrication processes

We present a subjective review of custom cellgeneration methods in the context of future advances instate-of-the-art digital circuit synthesis. In particular, wedescribe three opportunities for coupling circuitoptimization operations with the library developmentprocess. These operations include electrical optimization,technology mapping, and cell level place and route.

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1997/dac97/pdffiles/27_1.pdf

David P. Marple

Papers

CAD and simulation system for targeting IC designs to multiple fabrication processes

The future of custom cell generation in physical synthesis

Area-delay optimization of programmable logic arrays