Patent
CAD and simulation system for targeting IC designs to multiple fabrication processes
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TLDR
In this article, a generic CBA library represents several libraries for different process technologies and the resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies.Abstract:
Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. This generic CBA library represents several libraries for different process technologies. The resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies. Hence, only one design need be created and simulated. Generic design rule and parasitic parameters are then used to optimize the placement and routing of the generic design. The post-layout generic design is then simulated and verified using performance characteristics determined by a combination of the technologies. The accepted, generic post-layout design is then ported for each intended fabrication process to create the mask patterns associated with each fabrication process.read more
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References
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Patent
Automatic layout planner and a method for automatically creating a layout plan
Toshinori Watanabe,Sasaki Koji,Chizuko Yasunobu,Iizuka Yumiko,Yoshiaki Nagai,Toshiro Yamanaka,Minoru Yamakoshi,Takashi Tanaka +7 more
TL;DR: In this paper, a group of rules can be called from a knowledge base according to an intermediate layout plan generated in a data structure by a rule interpreter, which can be used for automatic layout planning without previously specifying place of each parts.
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TL;DR: In this paper, an improved automatic placement process for placing logic cells in a universal array is proposed, where unused basic units allocated to a given row are distributed along that row in a manner to reduce wiring congestion.