Showing papers by "David W Parent published in 2012"

Compact digital implementation of a quadratic integrate-and-fire neuron

Abstract: A compact fixed-point digital implementation of a quadratic integrate-and-fire (QIF) neural model was developed. Equations were derived to determine the minimum number of bits the digital QIF model requires to represent all four states of the QIF model and control the switching threshold of the output voltage. In addition, the equations were used to minimize the size of the multiplier used for the nonlinear squaring function, V2. These design equations were used to develop test vectors that could unambiguously show all four states of a digital QIF model. The FPGA implementation of the QIF model was shown to be computationally efficient, requiring only two fixed-point adders and one fixed-point multiplier.

Influence of Personality on a Senior Project Combining Innovation and Entrepreneurship

Abstract: A pilot multidisciplinary engineering senior design project incorporating innovation and entrepreneurship was undertaken at SanJose State University in the 2010–2011 academic year. The influence of personality domains described by the Big-Five(extraversion, agreeableness, conscientiousness, emotional stability, and openness) on individual student performance, groupexperience, and attitudes towards multidisciplinarity, after the conclusion of the first semester of a two semester experience, areexplored in this paper.

Design Optimization of Transistors Used for Neural Recording

Abstract: Neurons cultured directly over open-gate field-effect transistors result in a hybrid device, the neuron-FET. Neuron-FET amplifier circuits reported in the literature employ the neuron-FET transducer as a current-mode device in conjunction with a transimpedance amplifier. In this configuration, the transducer does not provide any signal gain, and characterization of the transducer out of the amplification circuit is required. Furthermore, the circuit requires a complex biasing scheme that must be retuned to compensate for drift. Here we present an alternative strategy based on the design approach to optimize a single-stage common-source amplifier design. The design approach facilitates in circuit characterization of the neuron-FET and provides insight into approaches to improving the transistor process design for application as a neuron-FET transducer. Simulation data for a test case demonstrates optimization of the transistor design and significant increase in gain over a current mode implementation.