Metal silicides have played an indispensable role in the rapid developments of microelectronics since PtSi was first used to improve the rectifying characteristics of diodes in early 1960s. This wo ...

Metal silicides in CMOS technology : Past, present, and future trends

Modulation spectroscopy is a powerful method for the study and characterization of a large number of semiconductor configurations, including bulk/thin film, microstructures (heterojunctions, quantum wells, superlattices, quantum dots), surfaces/interfaces and actual device structures in addition to semiconductor growth/processing. Furthermore, the influence of external perturbations such as temperature, electric fields, hydrostatic pressure, uniaxial stress, etc. can be investigated. This optical technique utilizes a very general principle of experimental physics, in which a periodically applied perturbation (either to the sample or probe) leads to sharp, derivative-like spectral features in the optical response of the system. Because of the richness of the derivative-like spectra, the information in the lineshape fits, room temperature performance and relative simplicity of operation this method is becoming increasingly more important as a tool to study these materials and structures. This article will review developments in the field during the last decade.

Modulation spectroscopy of semiconductors: bulk/thin film, microstructures, surfaces/interfaces and devices

The paradigm and the usage of CMOS are changing, and so are the requirements at all levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and density of integration, are subject to other prerogatives related to variability, manufacturability, power consumption/dissipation (mobile products!), mix of varied digital and analog/RF functions (system-on-chip integration), etc. Controllability of variations and static leakage will add to, and in certain products prevail, over speed and density. Implications at all levels are multiple and are more diverse than just speed and smallness. The goal of the authors has been to see the problem globally from the product level and to place its components in their true proportions. Therefore, we will start with drawing the product-level picture and placing it in a historical perspective. Next, we will review the state of the art, the requirements, and solutions at the level of materials, transistor, and technology. Detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented in this paper.

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

A technology roadmap for the electrical performance of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) is presented based on combining the results of various 1-D, 2-D, and 3-D technology computer-aided design (TCAD) simulation tools with geometry scalable compact modeling. The latter, including all known parasitic effects, enables the accurate determination of the figures of merit for both devices and selected benchmark circuits. The presented roadmap defines five major technology nodes with the maximum oscillation frequency of a typical high-frequency device structure as the main device design target under the constraints of various other parameters for generating the doping profiles and for defining the lateral scaling factors. An extensive and consistent set of technology and electrical parameters is provided along with the obtained scaling rules. The expected fabrication-related challenges and possible solutions for achieving the predicted performance are being discussed. It is hoped that the presented roadmap will be useful not only for foundries and equipment manufacturers but also for circuit and system designers enabling better predictions of the capability of SiGe–BiCMOS process technology for new millimeter-wave (mm-wave) and terahertz (THz) applications.

SiGe HBT Technology: Future Trends and TCAD-Based Roadmap

It is shown that the charge-pumping technique can be successfully applied to SOI structures, directly providing important and reliable information about the quality of both front- and back-gate interfaces. The possibility of performing measurements on a transistor level makes direct correlation with other MOS characteristics and material parameters possible. In particular, the ability of this technique to perform measurements on thin-film transistors and to separate the information from front and back gates makes it indispensable for characterization of advanced SOI CMOS structures. Although the technique was demonstrated only on 5- mu m channel length devices, it has sufficient sensitivity to be applicable to transistors of micrometer and submicrometer dimensions. Charge-pumping measurements on laser-recrystallized SOI MOSFETs showed that the front interface is only slightly deteriorated compared to that of bulk MOSFET devices, while the back interface is of a substantially lower quality, with about 10 times higher interface trap densities. >

Characterization of front and back Si-SiO/sub 2/ interfaces in thick- and thin-film silicon-on-insulator MOS structures by the charge-pumping technique

A 200-mm 0.35- m silicon-germanium hetero- junction bipolar transistor (SiGe HBT) technology involving epitaxially-aligned polysilicon emitters is described. The devices are shown to combine the high speed performances typical for poly-Si emitter SiGe base devices ( up to 70 GHz) and the low noise properties of monocrystalline emitter structures (noise figure-of-merit KB as low as m Statistical current gain data are used to demonstrate the manufacturability of this innovative SiGe HBT technology.

SiGe HBT Technology Using Epitaxially-Aligned Polysilicon Emitters

Photoreflectance study of strained (001) Si1−xGex/Si layers

Aspects of the selective deposition of TiSi2 by LRP-CVD for use in ULSI submicron technology

In this paper, we present a highly-performant PMOS transistor architecture featuring a buried strained SiGe layer (stressor) underneath the Si channel and in between the epitaxially grown Si S/D regions. This stressor together with the shallow trench isolation (STI) induces pseudo-biaxial compressive stress in small devices Si channel. A completely different behaviour compared to bulk-Si devices is shown. Transistors featuring a 50nm gate length, a 1.5nm physical gate oxinitride and an active area width of 0.28/spl mu/m demonstrate drive currents up to 740/spl mu/A//spl mu/m with only 48nA//spl mu/m Ioff at a supply voltage of 1.4V. Those results, regarding the oxide thickness, are in the range of the best ever reported. Moreover, this solution provides easy co-integration possibilities between HP, GP and LP (bulk-like or SON: silicon-on-nothing) devices on the same chip.

Didier Dutartre

Papers

SiGe HBT Technology Using Epitaxially-Aligned Polysilicon Emitters

Photoreflectance study of strained (001) Si1−xGex/Si layers

Aspects of the selective deposition of TiSi2 by LRP-CVD for use in ULSI submicron technology

Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS

Thermal stability of W on RTCVD Si1-xGex films