An arbitration technique for a split transaction bus (50) of a computer system obtains higher data throughput as a result of giving responders (62), e.g. memories, absolute priority over initiators (60), e.g. processors and I/O adapters, as a result of assigning all responders a higher priority than any initiator. Precedence is also given to retrying initiators which failed to complete a transaction because the module (52, 54) to which the transfer was addressed was busy. The requests from non-retrying initiators are temporarily rescinded to give precedence to the requests from retrying initiators. There is an absolute limit to the number of requests which a retrying module may make before it is granted mastership of the bus to accomplish its transfer. To accomplish the test-and-set and memory scrub transactions with a minimum time loss, the bus of the computer system creates a null conductivity cycle immediately following the cycle in which the address of the memory location to be tested and set or scrubbed, is selected.

Arbitration technique for a split transaction bus in a multprocessor computer system.

A method for redistributing the mastership of system resources among the processing nodes within the clustered computer system following a change in the system configuration, such as the failure of a processing node or the return to service of a failed processing node. The method includes the steps of: maintaining a set of hash buckets within each processing node; assigning each one of the resources to one of the hash buckets; and assigning a hash vector, determined through utilization of an N-way recursive algorithm, to each one of the hash buckets, each one of the hash vectors identifying the processing nodes within the clustered computer system in a predetermined sequence unique to the one of the hash buckets. Mastership of any system resource resides with the first processing node identified by the hash vector assigned to the hash bucket to which the system resource is assigned. Following the failure of a processing node, the method reassigns mastership of the system resources assigned to the set of hash buckets associated with a failed processing node the next processing node having an active state identified by the hash vector assigned to the set of hash buckets associated with the failed processing node. Mastership of the resources initially assigned to the set of hash buckets associated with the failed node is reassigned to the failed node upon return of the failed node to an active state.

Dynamic hashing method for optimal distribution of locks within a clustered system

A datagram messaging service for a distributed lock manager implemented on a clustered computer system including a plurality of processing nodes interconnected through a network. The messaging service establishes and maintains a plurality of virtual circuits between the processing nodes, a single virtual circuit connecting each pair of processing nodes within the clustered computer system. A distributed lock manager driver is included within each processing node, the driver including a communication service providing for the generation of datagrams comprising lock manager instructions for transmission to other processing nodes within the clustered computer system via said virtual circuits and also providing for the receipt of datagrams generated and transmitted by the other processing nodes.

Reliable datagram service provider for fast messaging in a clustered environment

A mechanism for determining when the contents of a block in a cache memory have been rendered stale by DMA activity external to a processor and for marking the block stale in response to a positive determination. The commanding unit in the DMA transfer, prior to transmitting an address, asserts a cache control signal which conditions the processor to receive the address and determine whether there is a correspondence to the contents of the cache. If there is a correspondence, the processor marks the contents of that cache location for which there is a correspondence stale.

Cache invalidate protocol for digital data processing system

A distributed shared-memory multiprocessor system capable of reducing a traffic on the shared bus, without imposing any constraint concerning the types of variables to be accessed in the parallel programs, such that a high system extensibility can be realized. The system is formed by a plurality of processor units coupled through a shared bus, where each processor unit comprises: a CPU; a main memory connected with the CPU through an internal bus, for storing a distributed part of data entries of a shared-memory of the system; a cache memory associated with the CPU and connected with the main memory through the internal bus, for caching selected data entries of the shared-memory; and a sharing management unit connected with the main memory and the cache memory through the internal bus, For interfacing the internal bus and the shared bus according to a sharing state for each data entry of the main memory and a cache state of each data entry of the cache memory.

Distributed shared-memory multiprocessor system with reduced traffic on shared bus

One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68). In this way, non-path accesses of a local memory can be permitted, yet proper invalidation of cache memories can be performed in a simple manner.

Dileep P. Bhandarkar

Papers

Cache invalidation mechanism for multiprocessor systems