A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.

Protocol for communication with dynamic memory

An arbitration technique for a split transaction bus (50) of a computer system obtains higher data throughput as a result of giving responders (62), e.g. memories, absolute priority over initiators (60), e.g. processors and I/O adapters, as a result of assigning all responders a higher priority than any initiator. Precedence is also given to retrying initiators which failed to complete a transaction because the module (52, 54) to which the transfer was addressed was busy. The requests from non-retrying initiators are temporarily rescinded to give precedence to the requests from retrying initiators. There is an absolute limit to the number of requests which a retrying module may make before it is granted mastership of the bus to accomplish its transfer. To accomplish the test-and-set and memory scrub transactions with a minimum time loss, the bus of the computer system creates a null conductivity cycle immediately following the cycle in which the address of the memory location to be tested and set or scrubbed, is selected.

Arbitration technique for a split transaction bus in a multprocessor computer system.

A method for redistributing the mastership of system resources among the processing nodes within the clustered computer system following a change in the system configuration, such as the failure of a processing node or the return to service of a failed processing node. The method includes the steps of: maintaining a set of hash buckets within each processing node; assigning each one of the resources to one of the hash buckets; and assigning a hash vector, determined through utilization of an N-way recursive algorithm, to each one of the hash buckets, each one of the hash vectors identifying the processing nodes within the clustered computer system in a predetermined sequence unique to the one of the hash buckets. Mastership of any system resource resides with the first processing node identified by the hash vector assigned to the hash bucket to which the system resource is assigned. Following the failure of a processing node, the method reassigns mastership of the system resources assigned to the set of hash buckets associated with a failed processing node the next processing node having an active state identified by the hash vector assigned to the set of hash buckets associated with the failed processing node. Mastership of the resources initially assigned to the set of hash buckets associated with the failed node is reassigned to the failed node upon return of the failed node to an active state.

Dynamic hashing method for optimal distribution of locks within a clustered system

An arbiter is provided for resolving contention on synchronous packet switched busses, including busses composed of a plurality of pipelined segments, to ensure that all devices serviced by such a bus are given fair, bounded time access to the bus and to permit such devices to fill all available bus cycles with packets. Flow control for shared memory multiprocessors is readily implemented with this arbiter because the arbiter supports different types of arbitration requests and the prioritization of such arbitration requests by type.

Arbitration of packet switched busses, including busses for shared memory multiprocessors

A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.

Method and apparatus for signaling between devices of a memory system

A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.

Bus device for use in a computer system having a synchronous bus

One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68). In this way, non-path accesses of a local memory can be permitted, yet proper invalidation of cache memories can be performed in a simple manner.

Cache invalidation mechanism for multiprocessor systems

Control of a communications path interconnecting separate devices in a digital computer system is provided by only two signals generated and received locally within each device on the path and asserted on a systems-wide basis on two separate lines of the path. The generation and utilization of the control signals is independent of the physical location of the devices on the path, and position-dependent delays in transmission of the signals from one device to another are avoided.

Bus-control mechanism

Control of a communications path interconnecting separate devices in a digital computer system is provided by only two signals generated (No ARB,BSY) and received locally within each device on the path and asserted on a systems- wide basis on two separate lines of the path. The generation and utilization of the control signals is independent of the physical location of the devices on the path, and position- dependent delays in transmission of the signals from one device to another are avoided.

Reinhard Schumann

Papers

Bus device for use in a computer system having a synchronous bus

Cache invalidation mechanism for multiprocessor systems

Bus-control mechanism

Control mechanism for multiprocessor system