Patent
Cache invalidation mechanism for multiprocessor systems
Bomba Frank C,Dileep P. Bhandarkar,J. J. Grady,Stanley A. Lackey,Jeffrey W. Mitchell,Reinhard Schumann +5 more
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TLDR
In this paper, the authors propose to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the Common Communications Path (68).Abstract:
One of a plurality of devices on a common communications path (68) has a local memory (54) that is accessible by other devices on the common communications path (68). Another device on the common communications path (68) may include a cache memory (190) that keeps copies of certain of the data contained by the local memory (54). If another device on the common communications path (68) accesses the local memory (54), the cache (190) is kept apprised of this fact by monitoring of the common communications path (68), and it sets an internal flag to indicate that the data involved may not be valid. However, the contents of memory 54 may also be accessed by means of a processor (50) without using the common communications path (68). Accordingly, provisions are made to send an invalidate signal over the common communications path (68) when a non-path access of the local memory (54) has been made to a location to which access was previously afforded over the common communications path ( 68). In this way, non-path accesses of a local memory can be permitted, yet proper invalidation of cache memories can be performed in a simple manner.read more
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References
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Patent
Multiprocessing system including a shared cache
TL;DR: In this article, the authors propose a control system for interlocking processors in a multiprocessing organization where each processor has its own high speed store in buffer (SIB) cache and each processor shares a common cache with the other processors.
Patent
Adaptive domain partitioning of cache memory space
TL;DR: In this article, a method of operation of a memory array for storage of records of differing predetermined sizes is disclosed which features division of the array into domains which are substantially integral multiples of the predetermined record sizes.
Patent
Shared virtual address translation unit for a multiprocessor system
Yasushi Fukunaga,Tadaaki Bandoh,Hidekazu Matsumoto,Ryosei Hiraoka,Jushi Ide,Takeshi Kato,Tetsuya Kawakami +6 more
TL;DR: In this paper, a virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed.
Patent
Cache locking controls in a multiprocessor
TL;DR: In this paper, a lock array is provided with bit positions corresponding to each line entry in an associated cache directory, and a replacement selection circuit is used to eliminate each locked line from being a replacement candidate in its congruence class in a set-associative store-in-cache in a multiprocessor (MP).
Patent
High speed buffer operation in a multi-processing system
TL;DR: In this paper is an interlocking scheme which permits multiprocessing in a shared storage configuration with each central processing unit (CPU) having a private high-speed buffer storage utilizing the store-in-buffer concept.
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