D
Dong-gun Park
Researcher at Samsung
Publications - 92
Citations - 1584
Dong-gun Park is an academic researcher from Samsung. The author has contributed to research in topics: Transistor & Field-effect transistor. The author has an hindex of 24, co-authored 92 publications receiving 1577 citations.
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Patent
Field effect transistors having multiple stacked channels
TL;DR: In this article, a pre-active pattern is constructed on a surface of a substrate and an active channel pattern is used to define at least one tunnel between adjacent channels, and a gate electrode is formed in the tunnels and surrounding the channels.
Patent
Method for forming a FinFET by a damascene process
TL;DR: In this paper, a gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layers are formed on the remaining portion of the active region where the gate electrode was not formed.
Journal ArticleDOI
High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer
Sung Dae Suk,Kyoung Hwan Yeo,Keun Hwi Cho,Ming Li,Yun Young Yeoh,Sung-young Lee,Sung-min Kim,Eun Jung Yoon,Min Sang Kim,Chang Woo Oh,Sung Hwan Kim,Dong-Won Kim,Dong-gun Park +12 more
TL;DR: A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/m for n-channel and 1.30 mA /m for p-channel TSNWFETs with mid-gap TiN metal gate.
Patent
Methods of forming fin field effect transistors using oxidation barrier layers and related devices
TL;DR: In this article, a method of forming a fin field effect transistor on a semiconductor substrate is described, where an oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer.
Patent
Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same
TL;DR: A fin field effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region there between vertically protruding from a semiconductor substrate.