Dong Li

TL;DR: A priority-based cache allocation (PCAL) that provides preferential cache capacity to a subset of high-priority threads while simultaneously allowing lower priority threads to execute without contending for the cache is proposed.

TL;DR: This paper proposes Iterative Path Prediction to address low next block prediction accuracy and low speculation rates, and proposes Exposed Operand Broadcasts to address the overhead of operand delivery for high fanout instructions by exposing a small number of broadcast operands in the ISA.

TL;DR: The study shows that composing multiple dual-issue cores (up to eight) provides performance scaling that is as energy-efficient as frequency scaling in a balanced microarchitecture, and is considerably more efficient than scaling the voltage to achieve additional performance once the maximum frequency at the minimum voltage is attained.

TL;DR: In this paper, the first message for each of the target instructions including selected information commonly shared by the target instruction is provided, and when two target instructions are located in different directions from one another relative to a router, the replicated messages are routed to the identified target instructions in the different directions.

TL;DR: A compiler optimization to reuse broadcast tags for instructions with non-overlapping broadcast live ranges, the speedup is further improved without spending more power, and the results show that this compiler-assisted hybrid token/broadcast model requires only eight architectural broadcasts per block, enabling highly efficient CAMs.