M
Mike O'Connor
Researcher at University of Texas at Austin
Publications - 54
Citations - 3207
Mike O'Connor is an academic researcher from University of Texas at Austin. The author has contributed to research in topics: Cache & Dram. The author has an hindex of 25, co-authored 53 publications receiving 2629 citations. Previous affiliations of Mike O'Connor include Nvidia & Sun Microsystems.
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Proceedings ArticleDOI
Cache-Conscious Wavefront Scheduling
TL;DR: This paper proposes Cache-Conscious Wave front Scheduling (CCWS), an adaptive hardware mechanism that makes use of a novel intra-wave front locality detector to capture locality that is lost by other schedulers due to excessive contention for cache capacity.
Journal ArticleDOI
Transparent offloading and mapping (TOM): enabling programmer-transparent near-data processing in GPU systems
Kevin Hsieh,Eiman Ebrahimi,Gwangsun Kim,Niladrish Chatterjee,Mike O'Connor,Nandita Vijaykumar,Onur Mutlu,Stephen W. Keckler +7 more
TL;DR: Extensive evaluations across a variety of modern memory-intensive GPU workloads show that TOM significantly improves performance compared to a baseline GPU system that cannot offload computation to 3D-stacked memories.
Journal ArticleDOI
PicoJava: a direct execution engine for Java bytecode
H. McGhan,Mike O'Connor +1 more
TL;DR: By the end of 1998, Java processors like Sun's microJava 701 should be available for evaluation from several licensees of the picoJava core technology, thus extending the useful range of Java bytecode programs to embedded environments.
Proceedings ArticleDOI
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
Kevin K. Chang,Abdullah Giray Yağlıkçı,Saugata Ghose,Aditya Agrawal,Niladrish Chatterjee,Abhijith Kashyap,Donghyuk Lee,Mike O'Connor,Hasan Hassan,Onur Mutlu +9 more
TL;DR: This paper takes a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by manufacturers.
Proceedings ArticleDOI
Cache coherence for GPU architectures
TL;DR: This paper describes a time-based coherence framework for GPUs, called Temporal Coherence (TC), that exploits globally synchronized counters in single-chip systems to develop a streamlined GPU coherence protocol, called TC-Weak.