Mechanical and chemical recycling of solid plastic waste.

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Waste Printed Circuit Boards recycling: an extensive assessment of current status

Partial scan design is divided into two stages: (1) critical cycle breaking, and (2) partial scan flip-flop selection with respect to conflict resolution. A multiple phase partial scan design method is introduced by combining circuit state information and conflict analysis. Critical cycles are broken using a combination of valid circuit state information and conflict analysis. It is quite cost-effective to obtain circuit state information via logic simulation, therefore, circuit state information is iteratively updated after a given number of partial scan flip-flops have been selected. Valid-state-based analysis may become ineffective to select scan flip-flops when cycles remaining in the circuit are not influential to testability. The method turns to the conflict resolution process using an intensive conflict-analysis-based testability measure of conflict. Sufficient experimental results are presented.

A multiple phase partial scan design method

On-chip linear decompression-based schemes have been widely adopted by industrial circuits nowadays to effectively reduce the ever increasing test data volume and test time. Though they can easily achieve relatively high compression ratio, there is a bound of effective compression ratio for these compression schemes. Prior work tried to address this problem by trying different compression architectures to identify this compression bound. However, they can not predict this compression bound efficiently. In this paper, we will first analyze the correlation between the effective compression ratio and the compression architecture, thus to predict that compression bound efficiently. In addition, this paper will also propose how to design the compression architecture for target effective compression ratio with one-pass calculation, which was usually done by a time-consuming try-and-error process as well in the current DFT flow. Experimental results show the accuracy of the prediction and the effectiveness of the compression architecture design.

Prediction of compression bound and optimization of compression architecture for linear decompression-based schemes

Test generation and fault simulation of path delay faults are very time-consuming. A new fault simulation method of fully enhanced scan designed circuits is proposed for path delay faults based on single stuck-at tests without circuit transformation. The proposed method identifies robustly and non-robustly testable paths first, for which a selected path circuit (SPC) is constructed. The SPC circuit contains no internal fanouts. Fault simulation of non-robustly testable paths is reduced to 3-valued logic simulation of the SPC circuit. Fault simulation is completed on the SPC circuit by only tracing the active part of SPC circuit. An effective fault dropping technique is also adopted based on the selective tracing scheme. The proposed fault simulation scheme is extended to that of robustly testable path delay faults. Experimental results confirm that the proposed fault simulator is exact. It is shown according to experimental results that the proposed fault simulator gets exact fault simulation results in very short time. Sufficient experimental results are presented to compare with previous methods on CPU time and accuracy.

Fast and effective fault simulation for path delay faults based on selected testable paths

A new weighted pseudo-random test generator called wPRPG is proposed for low-power launch-on-capture (LOC) transition delay fault testing. The low-power weighted PRPG is implemented by assigning different weights on the test enable signals and applying a gating technique. The new low-power PRPG can achieve much higher transition delay fault coverage in LOC delay testing than the conventional test-per-scan PRPG.

Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing*

The increasing power consumption during the chip testing process has become the bottleneck of chip production and testing for micro-nano VLSI circuits. Numerous low power design-for-testability (DfT) techniques have been proposed to deal with the test power problem, and segmented scan method was shown to be an efficient solution. We propose a new poweraware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time. Since enabling only a subset of scan flip-flops to capture test responses in one cycle compromises the fault coverage, we propose a new method to reduce the fault coverage loss. First, we use a more accurate notion, spoiled nodes, instead of violation edges used in previous works to analyse the ependency of flip-flops, then we use simulated annealing(SA) mechanism to find the best combination of these flip-flops while considering the clock trees' impact. To the best of our knowledge, this is the first work to make shift and capture power in a controllable way with minimum fault coverage loss, small test-data volume and no extra hardware overhead for at-speed transition fault test. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed method.

Dong Xiang

Papers

A multiple phase partial scan design method

Prediction of compression bound and optimization of compression architecture for linear decompression-based schemes

Fast and effective fault simulation for path delay faults based on selected testable paths

Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing*

A Novel Scan Segmentation Design for Power Controllability and Reduction in At-Speed Test