Mechanical and chemical recycling of solid plastic waste.

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

Waste Printed Circuit Boards recycling: an extensive assessment of current status

The interface delamination of waste plastic chip will seriously affect the value of their recycling reuse; therefore, it has been a hot issue in recycling researches of Waste Electrical and Electronic Equipment (WEEE) Based on the exponential cohesion theory, this paper has researched chip delamination and established the Cohesive Zone Model (CZM) of delamination crack for chip interface, as well as proposed a method which combined the experiment of crack surface observation and the simulation of fracture mechanics By employing this method, the CZM parameters of waste plastic chip interface have been obtained Based on the CZM, the simulation of waste plastic chip interface delamination has been made, and its results showed that: temperature and humidity factors have a significant impact on the chip delamination At last, the disassembly experiments of Waste Printed Circuit Boards (WPCB) have been made under different disassembly technology, and the delamination rate of resulting chips has been calculated Then this paper has analyzed the influence rule of different disassembly conditions on the chip delamination and verified the correctness of chip delamination simulation results, as well as proposed an optimized disassembly technology of WPCB for reducing plastic chip’s delamination Introduction With the rapid development of world economy, a large number of Waste Electrical and Electronic Equipment (WEEE) appeared each year, and caused tremendous pressure to the environment, then the recycling of WEEE has become a major issues causing social attention Countries all around the world have issued corresponding bill about WEEE processing  For example, the WEEE Directive issued by European Union in 2003 cleared rules for ten classes of recovery and regeneration utilization of WEEE Printed Circuit Board (PCB) is the important material for classification processing after dismantling the WEEE, "the National Hazardous Waste List" of China clearly stipulates that PCB components are T-class hazardous wastes Therefore, studying the recycling method is of great significance Component reuse is an effective method to achieve the high value recycling of Waste Printed Circuit Boards (WPCB), and is the current hot research spot Study shows that the design life of components is 500000 hours, while the average service life of WEEE in developed country is only 20000 hours According to the Bathtub Curve theory of components invalidation, the component is in the optimal period of quality, and has high reuse value  Guo Xiuying et al researched the reusability of waste plastic chip through experimental method in 2009, then put forward that the qualified rate can be up to 98% as long as the recycling way of waste plastic chip is reasonable and normative, and it could make very high reuse value The delamination damage of waste plastic chip is a common problem which influences chips’ reuse value and reliability, so the research of chip interface delamination has been the core content in the waste plastic chip reusability study Aiming at the interface delamination fracture problems of waste plastic chip, the exponential Cohesive Zone Model (CZM) was used to analyze delamination crack of two phase interface in chip interior, and the chip interface delamination was analyzed by adopting finite element simulation method with the CZM as a guide Finally, the simulation results were verified to be International Power, Electronics and Materials Engineering Conference (IPEMEC 2015) © 2015 The authors Published by Atlantis Press 720 effective through the WPCB disassembly experiment, and concrete countermeasures of WPCB disassembly technology to reduce the chip delamination were put forward The Cohesive Zone Model Traditional interface delamination fracture research was conducted using fracture mechanics simulation method, thus it needed to set the preset crack in simulation model Due to the position and size of preset crack were set subjectively, it often brought great influence on the accuracy of calculation results  In addition, we can also use the cohesion theory to describe the fracture behavior of material The crack formation and extension phenomenon is analyzed with the tension displacement law of cohesion theory, and it doesn't need preset crack in simulation process, so this is very suitable for the fracture problems of fixed crack propagation path The delamination phenomenon of plastic chip mainly occurs in the interface between different materials, and the crack formation and extension path is relatively stationary Therefore, the cohesion theory method was adopted to study the delamination fracture problems of plastic chip in this paper In the delamination fracture process of plastic chip, a transition zone generates in the interface between two phase materials This paper used the edge-opened crack as example to study the fracture process, as shown in Fig1(a) There is a transition zone between the original interface and free surface in the tensile fracture zone, which is called cohesive zone The mechanical properties of material in cohesive zone are different from other interfaces of plastic chip For the mechanical properties of cohesive zone, it is described with the tension displacement law Among numerous cohesion models, the tension displacement law of exponential CZM most conforms to the Van Der Waals force form, and gets high accuracy to solve the problems of composite interface fracture [7,  So the exponential CZM was adopted to study the interface delamination fracture problems of plastic chip in this paper Fig1 Cohesive zone of plastic chip delamination interface The cohesive zone of delamination crack in plastic chip is shown in Fig1(b), making an analysis of one point in the cohesive zone, the received tension of the point can be decomposed to a normal tension Pn which is perpendicular to the interface and a tangential tension Pt which is parallel to the interface The interface’s fracture displacement δ can be also decomposed to a normal displacement δn and a tangential displacement δt The relation between the fracture energy φ(δ) of exponential CZM and the interface’s fracture displacement δ is shown in Eq1

Research Based on Cohesive Zone Model for Interface Delamination of Waste Plastic Chip

A global design for testability algorithm is offered in this paper. First, a test point candidate set is obtained to simplify the test point placement problem; the principle of selective tracing is offered to get a sequential test point placement solution, which is used as the initial solution of the global algorithm. Using this initial value, abranch & bound algorithm is then offered to obtain a global design for testability solution. Finally, a new test length analyser is offered to evaluate the global design for testability.

GLOBAL: A design for random testability algorithm

A non-scan design for testability method for RTL circuits based on conflict analysis is proposed. Conflict analysis is presented based on a new 5-valued system to estimate testability of data paths. New test point structures for RTL circuit design for testability are introduced. Nonscan design for testability is proposed based on conflict resolution. Unlike most of the previous methods, our method considers testability of data paths and the controller simultaneously. Different classes of test points can be inserted into data paths and the controller. Intensive techniques are presented to connect extra inputs of test points with PI ports, which avoids generating reconvergent fanouts that cause new conflicts.

Non-scan design for testability for mixed RTL circuits with both data paths and controller via conflict analysis

The design of a vector showerhead in a vertical reactor involves thousands of holes on the showerhead face plate and mass transport in the reactor, and the design variables and objective are always spatial related continuous characteristic, so the discretized sequence of the design variables has too many degrees of freedom that the needed sampling points of a design of experiment or heuristic algorithm methods are hardly acceptable. In order to solve this problem, a profile error feedback (PEF) optimization method was proposed. This method employed a loop-iteration-approximation mode, and started from a guessed initial model, and then fed back the profile error of design objective, according to a weight function, to continually adjusted the design variable sequence to make the gas flow uniformity in the new model continually approximate the perfect one. The optimization case of a vector showerhead system shown that the non-uniformity of the gas flow was reduced from 0.36% to 0.03% under a typical process condition.

The Profile Error Feedback Optimization for the Design of a Showerhead System Controlling Gas Flow Uniformity in a Thin-Film Reactor

A new deadlock-free partially adaptive routing algorithm is proposed for 2 ? dimensional (2D) tori with only two virtual channels. The deadlock avoidance technique is presented based on a new turn model for 2D tori. In order to avoid cyclic channel dependencies completely, we propose the new odd-even turn model for 2D tori. The new model is an improved algorithm of the original turn model, and sets some constraints for some special turns. As far as we know, there is no existing algorithm for deadlock-free partially adaptive routing in 2D tori using only two virtual channels in the literature up to now. Sufficient simulation results are presented to demonstrate the effectiveness of the proposed algorithm by comparing with several previous methods.

Dong Xiang

Papers

Research Based on Cohesive Zone Model for Interface Delamination of Waste Plastic Chip

GLOBAL: A design for random testability algorithm

Non-scan design for testability for mixed RTL circuits with both data paths and controller via conflict analysis

The Profile Error Feedback Optimization for the Design of a Showerhead System Controlling Gas Flow Uniformity in a Thin-Film Reactor

Deadlock-Free Adaptive Routing in 2D Tori with a New Turn Model