An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Integrated Circuit Devices and Methods and Apparatuses for Designing Integrated Circuit Devices

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Cell circuit and layout with linear finfet structures

A system and method for configuring routing resources of a programmable logic device are presented in various embodiments. In one embodiment, a first function is provided that automatically generates configuration bits for configuration of routing resources to connect a source to a sink. The input parameters to the to the first function include the source and the sink. A second function is provided to automatically generate configuration bits for configuration of routing resources that connect a source to a plurality of sinks. The second function is responsive to input parameters specifying the source and plurality of sinks. Additional program interfaces are provided and each provides various controls over the routing process.

Run-time routing for programmable logic devices

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A gate array book layout for an integrated circuit chip is disclosed in which a local interconnect layer provides N-well and P-well contact straps extending substantially along the entire width of said gate array book across the top and bottom edges thereof. This enables efficient electrical connections between the various connection points located within the book. In particular, primarily vertical strips of local interconnect are used to connect contact points which exist at or near the same layer as the local interconnect layer. By using local interconnect in this manner, metal-1 layer usage is significantly reduced thereby allowing for a more efficient integrated circuit chip design.

Integrated circuit chip having gate array book personalisation using local interconnect

A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Method of combining gate array and standard cell circuits on a common semiconductor chip

A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low modulus dielectric layers (216, 222, 232) are disposed over a workpiece (212). Support structures (218, 226, 236) are formed in the low modulus dielectric layers (216, 222, 232), and support vias (224, 234) are formed between the support structures (218, 226, 236). A high modulus dielectric film (220, 230) is disposed between each low modulus dielectric layer (216, 222, 232), and a high modulus dielectric layer (256) is disposed over the top low modulus dielectric layer (232). Contact pads (204) are formed in the high modulus dielectric layer (256). Each support via (234) within the low modulus dielectric layer (232) resides directly above a support via (224) in the underlaying low modulus dielectric layer (222), to form a plurality of via support stacks within the low modulus dielectric layers (216, 222, 232).

Support structures for wirebond regions of contact pads over low modulus materials

A method for wiring IC chips such that electromigration criteria are met while minimizing the effect on overall chip wireability. A technique to optimize the width of automatically routed wire segments so that these widths are adequate to support the electromigration current on that net as a function of the capacitive loading of the net itself.

Wiring design tool improvement for avoiding electromigration by determining optimal wire widths

Disclosed herein is a system for controlling power supply voltage to an on-chip power distribution network. The system incorporates a programmable on-chip sensing network that can be selectively connected to the power distribution network at multiple locations. When the sensing network is selectively connected to the power distribution network at an optimal sensing point, a local voltage feedback signal from that optimal sensing point is generated and used to adjust the power supply voltage and, thus, to manage voltage distribution across the power distribution network. Additionally, the system incorporates a policy for managing the voltage distribution across the power distribution network, a means for profiling voltage drops across the power distribution network and a means for selecting the optimal sensing point based on the policy and the profile. Another embodiment of the system can further control power supply voltages to multiple power distribution networks on the same chip.

Douglas W. Kemerer

Papers

Integrated circuit chip having gate array book personalisation using local interconnect

Method of combining gate array and standard cell circuits on a common semiconductor chip

Support structures for wirebond regions of contact pads over low modulus materials

Wiring design tool improvement for avoiding electromigration by determining optimal wire widths

Programmable on-chip sense line