Patent
Method of combining gate array and standard cell circuits on a common semiconductor chip
Elliot L Gould,Douglas W. Kemerer,Lance A Mcallister,Ronald A. Piro,Guy R Richardson,Deborah A Wellburn +5 more
TLDR
In this paper, a method and semiconductor structure for intermixing circuits of two or more different cell classes on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes.Abstract:
A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.read more
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Patent
Semiconductor integrated circuit with mixed gate array and standard cell
Nobuo Fudanuki,Toshikazu Sei +1 more
TL;DR: In this article, a semicustom ASIC, in which a plurality of standard cell rows are arranged on the same chip, has been proposed, where a changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern.
Patent
Method for fabricating wafer-scale integration wafers and method for utilizing defective wafer-scale integration wafers
TL;DR: In this article, the authors proposed a method to detect and correct errors generated within the discrete memory sections where wafer-scale integration manufacturing is successful, where fuses within the test circuitry are provided and selectively blown to isolate the inoperative areas from each respective memory section, thereby increasing the yield of operable circuitry on the wafer.
Patent
Tool suite for the rapid development of advanced standard cell libraries
TL;DR: In this article, a library tool suite supplements conventional design tools to increase the speed, automation and accuracy of creating physical designs for a library of cells to be used in chip designs, including a post operations tool, an audit tool, a custom interface, a setup file and a place and route model preparation utility.
Patent
Structure and method of fabricating high-density trench-based non-volatile random access SONOS memory cells for SOC applications
TL;DR: In this paper, a two-transistor silicon-oxide-nitride-oxideoxide-semiconductor (2-Tr SONOS) nonvolatile memory cells with randomly accessible storage locations as well as method of fabricating the same, is presented.
Patent
Global wiring by removal of redundant paths
TL;DR: In this paper, a method for interconnecting nodes in each of a number of nets is proposed, which involves generating initial zones for all nets and determining cumulative demand for path spaces needed by these initial zones, then compared with the supply, and scores are determined for the paths of the initial zones.
References
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Patent
Integrated circuit having predetermined outer to inner cell pitch ratio
TL;DR: In this paper, the ratio of the pitch length of the outer cells to the pitch lengths of the inner power supply lines or the inner cells is determined by a ratio of two integers.
Patent
Semiconductor integrated circuit device
TL;DR: In this paper, the second and third wiring layers, which are connected to a drain power source and a source power source on a first poly-silicon wiring layer, also serve a role of a gate electrode of two-input NOR gate, are arranged separately each other.
Patent
CMOS/SOS transistor gate array apparatus
TL;DR: In this article, a universal gate array is illustrated using a specific pattern of CMOS transistors in an array which provides a high degree of board utilization in the layout of small runs of integrated circuits where the high cost of completely customized boards is unacceptable.
Patent
CMOS Cell array with transistor isolation
TL;DR: In this paper, a new technique for forming CMOS custom logic circuits is disclosed wherein standard cells (10,12,14) are used and the prior art technique of field oxide isolation (16) is replaced with transistor isolation (68-71).
Patent
Complementary metal-oxide semiconductor integrated circuit device of master slice type
TL;DR: In this article, a complementary metal-oxide semiconductor master slice integrated circuit comprises a plurality of basic cells (41, 141, 42, 142, 142; ) in an internal functional gate region (22), each basic cell, which is a basic repetition unit, including a single P-channel metal oxide semiconductor and a single N-channel MOS semiconductor, are disposed linearly with respect to each other through an electrical isolation region.