The paper surveys a decade of R&D on coarse grain reconfigurable hardware and related CAD, points out why this emerging discipline is heading toward a dichotomy of computing science, and advocates the introduction of a new soft machine paradigm to replace CAD by compilation.

A decade of reconfigurable computing: a visionary retrospective

This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software.

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System-level power optimization: techniques and tools

The multiprocessor system-on-chip (MPSoC) uses multiple CPUs along with other hardware subsystems to implement a system. A wide range of MPSoC architectures have been developed over the past decade. This paper surveys the history of MPSoCs to argue that they represent an important and distinct category of computer architecture. We consider some of the technological trends that have driven the design of MPSoCs. We also survey computer-aided design problems relevant to the design of MPSoCs.

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Multiprocessor System-on-Chip (MPSoC) Technology

We present a survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems. The optimizations are targeted directly or indirectly at the memory subsystem, and impact one or more out of three important cost metrics: area, performance, and power dissipation of the resulting implementation.We first examine architecture-independent optimizations in the form of code transoformations. We next cover a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity, ranging from register files to on-chip memory, data caches, and dynamic memory (DRAM). We end with memory addressing related issues.

Data and memory optimization techniques for embedded systems

1. DTSE in Programmable Architectures. 2. Related Compiler Work on Data Tranfer and Storage Management. 3. Global Loop Transformations. 4. System-Level Storage Requirements Estimation. 5. Automated Data Reuse Exploration Techniques. 6. Storage Cycle Budget Distribution. 7. Cache Optimization. 8. Demonstrator Designs. 9. Conclusions and Future Work. References. Bibliography. Index.

Data Access and Storage Management for Embedded Programmable Processors

Video and image processing applications deal with large amounts of data which have to be stored and transferred. As the initial system specification describing these data manipulations heavily influences the final memory organization and hierarchy, there is a clear need for exploration support. We believe that the emphasis should lie on fast but accurate estimation and on the high-level steering of the involved system transformations. In this paper, a system exploration environment called ATOMIUM, is presented that supports these requirements. To illustrate the effectiveness of our approach, two realistic demonstrators are worked out and design results are described.

Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems

A program transformation strategy is presented that is able to reduce the buffer size and power consumption for a relatively large class of (pseudo)regular data-dominated signal processing algorithms. Our methodology is targeted toward an implementation on programmable processors, but most of the principles remain valid for a custom processor implementation. As power and area cost are crucial in the context of embedded multimedia applications, this strategy can be very valuable. The feasibility of our approach is demonstrated on a representative high-speed video processing algorithm for which we obtain a substantial reduction of the area and power consumption compared to the classical approaches.

Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems

In this paper, several DSP system design principles are presented which are valid for a large class of memory-intensive algorithms Our main focus lies on the optimization of the memory and I/O, since these are dominant cost factors in the domain of video and imaging applications This has resulted in several formalizable mapping principles, which allow to prevent the memory from becoming a bottleneck First, it as shown that for this class of applications, compile-time data caching decisions not only have a large effect on the performance, but also can have an even larger effect on the overall system cost and power consumption This is illustrated by means of experiments in which the whole range of no cache up to large cache sizes is scanned Next, it is shown that when enforcing constant I/O rates to reduce buffer sizes, the area gain may be far more important than the small performance decrease associated with it A technique to achieve this in an efficient way is proposed The main test-vehicle which is used throughout the paper to demonstrate our approach is the class of motion estimation type algorithms

Memory organization for video algorithms on programmable signal processors

Mapping real-time motion estimation type algorithms to memory efficient, programmable multi-processor architectures

Publisher Summary This chapter presents an architectural template that is able to execute the full search motion estimation algorithm or other similar video or image processing algorithms in real time. In video applications, several block-oriented local-neighborhood-dependent algorithms with simple control flow are used. The architecture is based on a set of programmable video signal processors (VSP's). It is also possible to integrate everything on a chip set using VSP cores. Due to the programmability, the system is very flexible and can be used for emulation of other similar block-oriented, local-neighborhood algorithms. The architecture can be easily divided into several partitions, without data-exchange between partitions. Special attention is paid to memory size and transfer optimization, which are dominant factors for both area and power cost. Block-oriented video algorithms typically have a lot of inherent parallelism, and are therefore, well suited for mapping on parallel architectures. These architectures are well suited for mass production, but they generally lack flexibility and/or programmability and they are not extendible with off-the-shelf components. Although, the architecture presented here has been designed for motion estimation (ME), it is fully programmable and parameterizable and can be used for emulation of similar algorithms. The problem of mapping algorithms on programmable weakly parallel architectures with distributed memories has been studied extensively already. However, most of these techniques are oriented to medium throughputs and/or algorithms with a limited amount of shared data. The chapter concludes that a detailed analysis of the data flow and a novel tuned choice of the bus architecture can lead to a significant reduction of the memory requirements and the number of transfers.

E. De Greef

Papers

Optimization of memory organization and hierarchy for decreased size and power in video and image processing systems

Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems

Memory organization for video algorithms on programmable signal processors

Mapping real-time motion estimation type algorithms to memory efficient, programmable multi-processor architectures

A Memory Efficient, Programmable Multi-Processor Architecture for Real-Time Motion Estimation Type Algorithms