Proceedings ArticleDOI
Memory organization for video algorithms on programmable signal processors
E. De Greef,F. Catthoor,H. De Man +2 more
- pp 552-557
TLDR
In this paper, several DSP system design principles are presented which are valid for a large class of memory-intensive algorithms, and it is shown that for this class of applications, compile-time data caching decisions not only have a large effect on the performance, but also can have an even larger impact on the overall system cost and power consumption.Abstract:
In this paper, several DSP system design principles are presented which are valid for a large class of memory-intensive algorithms Our main focus lies on the optimization of the memory and I/O, since these are dominant cost factors in the domain of video and imaging applications This has resulted in several formalizable mapping principles, which allow to prevent the memory from becoming a bottleneck First, it as shown that for this class of applications, compile-time data caching decisions not only have a large effect on the performance, but also can have an even larger effect on the overall system cost and power consumption This is illustrated by means of experiments in which the whole range of no cache up to large cache sizes is scanned Next, it is shown that when enforcing constant I/O rates to reduce buffer sizes, the area gain may be far more important than the small performance decrease associated with it A technique to achieve this in an efficient way is proposed The main test-vehicle which is used throughout the paper to demonstrate our approach is the class of motion estimation type algorithmsread more
Citations
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Journal ArticleDOI
Multiprocessor System-on-Chip (MPSoC) Technology
TL;DR: The history of MPSoCs is surveyed to argue that they represent an important and distinct category of computer architecture and to survey computer-aided design problems relevant to the design of MP soCs.
Journal ArticleDOI
Data and memory optimization techniques for embedded systems
Preeti Ranjan Panda,Francky Catthoor,Nikil Dutt,Koen Danckaert,Erik Brockmeyer,Chidamber Kulkarni,A. Vandercappelle,Per Gunnar Kjeldsberg +7 more
TL;DR: A survey of the state-of-the-art techniques used in performing data and memory-related optimizations in embedded systems, covering a broad spectrum of optimization techniques that address memory architectures at varying levels of granularity.
BookDOI
Data Access and Storage Management for Embedded Programmable Processors
Francky Catthoor,Koen Danckaert,Chidamber Kulkarni,Erik Brockmeyer,Per Gunnar Kjeldsberg,Tanja Van Achteren,Thierry Omnes +6 more
TL;DR: DTSE in Programmable Architectures and Related Compiler Work on Data Tranfer and Storage Management, and Automated Data Reuse Exploration Techniques.
Journal ArticleDOI
Codesign of embedded systems: status and trends
TL;DR: It is argued that new methodologies and AD tools support an integrated hardware software codesign process that begins before the system architecture is finalised.
Journal ArticleDOI
Memory data organization for improved cache performance in embedded processor applications
TL;DR: This work presents techniques that take into account the parameters of the data caches for organizing scalar and array variables declared in embedded code into memory, with the objective of improving data cache performance.
References
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Array architectures for block matching algorithms
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TL;DR: In this paper, a description of VLSI architectures for block-matching algorithms utilizing systolic array processors is given, and a well-known mapping procedure has been applied to derive the array processors from the algorithm.
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Parameterizable VLSI architectures for the full-search block-matching algorithm
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TL;DR: In this article, the authors propose a VLSI implementation of the full-search block-matching algorithm using linear arrays in conjunction with compact memory blocks based on three-transistor cells.
Journal ArticleDOI
An efficient and simple VLSI tree architecture for motion estimation algorithms
TL;DR: A low-latency, high-throughput tree architecture that implements both the full-search block-matching algorithm and the three-step hierarchical search algorithm in motion estimation is proposed and is suitable for VLSI implementation.
Proceedings ArticleDOI
Global communication and memory optimizing transformations for low power signal processing systems
TL;DR: The crucial impact of memory related power consumption on the global system power budget, in particular for multi-dimensional real-time signal processing subsystems, is illustrated and several ways to reduce them are proposed.