A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-2/sup 2/ algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-2/sup 2/ algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log/sub 4/N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL.

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A new approach to pipeline FFT processor

The FFT processor is one of the key components in the implementation of wideband OFDM systems. Architectures with a structured pipeline have been used to meet the fast, real-time processing demand and low-power consumption requirement in a mobile environment. Architectures based on new forms of FFT, the radix-2/sup i/ algorithm derived by cascade decomposition, is proposed. By exploiting the spatial regularity of the new algorithm, the requirement for both dominant elements in VLSI implementation, the memory size and the number of complex multipliers, have been minimized. Progressive wordlength adjustment has been introduced to optimize the total memory size with a given signal-to-quantization-noise-ratio (SQNR) requirement in fixed-point processing. A new complex multiplier based on distributed arithmetic further enhanced the area/power efficiency of the design. A single-chip processor for 1 K complex point FFT transform is used to demonstrate the design issues under consideration.

Designing pipeline FFT processor for OFDM (de)modulation

The design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-2/sup 2/ algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 /spl mu/m CMOS technology and takes an area of 40 mm/sup 2/. With 3.3 V power supply, it can compute 2/sup n/, n=0, 1, ..., 10 complex point forward and inverse FFT in real time with up to 30 MHz sampling frequency. The SQNR is above 50 dB for white noise input.

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Design and implementation of a 1024-point pipeline FFT processor

The appearance of radix-22 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-22 was extended to radix-2k . However, radix-2k was only proposed for single-path delay feedback (SDF) architectures, but not for feedforward ones, also called multi-path delay commutator (MDC). This paper presents the radix-2k feedforward (MDC) FFT architectures. In feedforward architectures radix-2k can be used for any number of parallel samples which is a power of two. Furthermore, both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this, the designs can achieve very high throughputs, which makes them suitable for the most demanding applications. Indeed, the proposed radix-2k feedforward architectures require fewer hardware resources than parallel feedback ones, also called multi-path delay feedback (MDF), when several samples in parallel must be processed. As a result, the proposed radix-2k feedforward architectures not only offer an attractive solution for current applications, but also open up a new research line on feedforward structures.

/pdf/pipelined-radix-2-k-feedforward-fft-architectures-5dku5xiwia.pdf

Pipelined Radix- $2^{k}$ Feedforward FFT Architectures

Large-scale single-frequency networks are now being considered in Europe as very promising network topologies to achieve drastic savings in spectrum usage for digital terrestrial television transmission. Such networks are possible using the COFDM system, with large guard intervals (more than 200 /spl mu/s) to absorb long echoes. In order to limit the spectral efficiency loss to about 20%, very long size fast Fourier transforms (up to 8 K complex points) have to be performed in real time for the demodulation of every COFDM symbol (every 1 ms). This paper presents the first VLSI single chip dedicated to the computation of direct or inverse fast Fourier transforms of up to 8192 complex points. Due to its pipelined architecture, it can perform an 8 K FFT every 400 /spl mu/s and a 1 K FFT every 50 /spl mu/s. All the storage is onchip, so that no external memories are required. A new internal result scaling technique, called convergent block floating point, has been introduced in order to minimize the required storage for a given quantization noise, The chip, 1 cm/sup 2/ large with 1.5 million transistors, has been designed in a 3.3 V-0.5 /spl mu/m triple-level metal CMOS process and is fully functional. The 8 K complex FFT function could therefore be introduced in the coming years in digital terrestrial TV receivers at low cost. >

A fast single-chip implementation of 8192 complex point FFT

The development is described of a semicustom delay commutator circuit to support the implementation of high-speed fast Fourier transform processors based on the radix 4 pipeline FFT algorithm of J.H. McClellan and R.J. Purdy (1978). The delay commutator is a 108000-transistor circuit comprising 12288 shift register stages and approximately 2000 gates of random logic realized with 2.5-micrometer design rule CMOS standard cell technology. It operates at a 10-MHz clock rate, which processes data at a 40-MHz rate. The delay commutator is suitable for implementing processors that compute transforms of 16, 64, 256, 1024, and 4096 (complex) points. It is implemented as a 4-bit-wide data slice to facilitate cocatenation to accommodate common data word sizes and to use a standard 48-pin dual-in-line package.

E.E. Swartzlander

Papers

A radix 4 delay commutator for fast Fourier transform processor implementation