Edgar A. León

TL;DR: A scalable simulator that couples a cycle-accurate node simulator with a supercomputer network model and shows its suitability for architecture research by evaluating the impact of cache injection on parallel application performance.

TL;DR: This work proposes HpMC, a new memory controller design that combines the best aspects of existing management policies to improve performance and energy, and creates HMsim, an infrastructure that enables n-level, heterogeneous memory studies by leveraging existing memory simulators.

TL;DR: This paper showcases the use of simulations to compare the impact of design options on representative production HPC applications, libraries, and multi-job workloads and presents advances in the TraceR-CODES simulation framework that enable this analysis and evaluates its prediction accuracy against experiments on a production fat-tree network.

TL;DR: A systematic study that characterizes applications with an emphasis on communication requirements, identifying a representative set of applications from a U.S. Department of Energy laboratory, and characterizing their communication requirements provided key insights into the procurement of next generation commodity systems.

TL;DR: It is shown that cache injection provides significant advantages over data prefetching by reducing the pressure on the memory controller by up to 96% and injection policies to determine when and where to inject data are proposed.