E
Elvira Teran
Researcher at Intel
Publications - 9
Citations - 253
Elvira Teran is an academic researcher from Intel. The author has contributed to research in topics: Cache & Speedup. The author has an hindex of 5, co-authored 7 publications receiving 148 citations. Previous affiliations of Elvira Teran include Texas A&M International University & Texas A&M University.
Papers
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Proceedings ArticleDOI
Perceptron learning for reuse prediction
TL;DR: Perceptron learning for reuse prediction with perceptron learning greatly improves accuracy over previous work and translates directly into performance in single-thread workloads.
Proceedings ArticleDOI
Perceptron-based prefetch filtering
TL;DR: Perceptron-based Prefetch Filtering (PPF) is introduced as a way to increase the coverage of the prefetches generated by an underlying prefetcher without negatively impacting accuracy, and improves performance on a memory-intensive subset of the SPEC CPU 2017 benchmarks.
Proceedings ArticleDOI
Multiperspective reuse prediction
Daniel A. Jimenez,Elvira Teran +1 more
TL;DR: The technique is demonstrated using a placement, promotion, and bypass optimization that outperforms state-of-the-art policies using a low overhead and the accuracy of the multiperspective technique is superior to previous work.
Proceedings ArticleDOI
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy
Jinchun Kim,Elvira Teran,Paul V. Gratz,Daniel A. Jimenez,Seth H. Pugsley,Christopher B. Wilkerson +5 more
TL;DR: This paper proposes a holistic cache management technique called Kill-the-PC (KPC) that overcomes the weaknesses of traditional prefetching and replacement policy algorithms and removes the need to propagate the PC through entire on-chip cache hierarchy while providing a holistic caches management approach with better performance.
Proceedings ArticleDOI
Minimal disturbance placement and promotion
TL;DR: It is shown that minimal disturbance policies can reduce the frequency of a costly read-modify-write cycle for replacement state, making them potentially suitable for future work in DRAM caches.