Elyar E. Gasanov

TL;DR: In this article, a method for routing nets in an integrated circuit design, comprising the steps of dividing the integrated circuit with lines in first direction and lines in second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in a second direction.

TL;DR: In this article, the first routing graph is formed with vertices corresponding to locations where lines in the first and second groups of substantially parallel lines in a first direction cross, and nets are globally routed as a function of the routing graph.

TL;DR: In this paper, a method for routing a net on an integrated circuit device, comprising the steps of creating a list of basis elements of the net, said basis elements being defined by a predetermined size limitation, determining a complexity value for each basis element as a function of the distance between pins in the basis element, forming a hypertree for the net as function of complexity values of basis element so determined.

TL;DR: In this article, the authors propose a heuristic algorithm and reordering of the buffers of the clock domain to balance clock delays in the domain, and to equalize clock delays of several domains of a group that have timing paths between them.

TL;DR: In this paper, a method of synthesizing a clock tree for an integrated circuit design is described, which includes the steps of constructing an initial balanced clock tree, calculating a clock arrival time for each clock driven cell in the initial clock tree and performing a timing analysis from the clock arrival times calculated for each Clock driven cell.