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Emilio Leonardi

Researcher at Polytechnic University of Turin

Publications -  299
Citations -  6513

Emilio Leonardi is an academic researcher from Polytechnic University of Turin. The author has contributed to research in topics: Scheduling (computing) & Network packet. The author has an hindex of 43, co-authored 299 publications receiving 6268 citations. Previous affiliations of Emilio Leonardi include Universidade Tecnológica Federal do Paraná, Medianeira & University of Turin.

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Temporal locality in today's content caching: why it matters and how to model it

TL;DR: This paper proposes a new parsimonious traffic model, named the Shot Noise Model (SNM), that enables users to natively capture the dynamics of content popularity, whilst still being sufficiently simple to be employed effectively for both analytical and scalable simulative studies of caching systems.
Proceedings ArticleDOI

A unified approach to the performance analysis of caching systems

TL;DR: In this paper, the authors propose a unified methodology to analyse the performance of caches (both isolated and interconnected), by extending and generalizing a decoupling technique originally known as Che's approximation, which provides very accurate results at low computational cost.
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A unified approach to the performance analysis of caching systems

TL;DR: In this paper, the authors propose a unified methodology to analyse the performance of caches (both isolated and interconnected), by extending and generalizing a decoupling technique originally known as Che's approximation, which provides very accurate results at low computational cost.
Proceedings ArticleDOI

Bounds on average delays and queue size averages and variances in input-queued cell-based switches

TL;DR: A general methodology is developed, mainly based upon Lyapunov functions, to derive bounds on average delays, and on queue size averages and variances of complex systems of queues of input-buffered, cell-based switch and router architectures.
Journal ArticleDOI

On the stability of input-queued switches with speed-up

TL;DR: This work considers cell-based switch and router architectures whose internal switching matrix does not provide enough speed to avoid input buffering and proposes several classes of scheduling algorithms whose stability properties are studied using analytical techniques mainly based upon Lyapunov functions.