Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

Rules for determining a compact circuit model consisting of four resistors and three inductors to accurately predict the skin effect have been developed. The circuit is easily constructed from the geometry, producing a response that matches exact results over a frequency range from dc to very high frequencies.

Compact equivalent circuit model for the skin effect

The rapid growth of the electrical modeling and analysis of the interconnect structure, both at the electronic chip and package level, can be attributed to the increasing importance of the electromagnetic properties of the interconnect circuit on the overall electrical performance of state-of-the-art very large scale integration (VLSI) systems. With switching speeds well below 1 ns in today's gigahertz processors, and VLSI circuit complexity exceeding the 100 million transistors per chip mark, power and signal distribution is characterized by multigigahertz bandwidth pulses propagating through a tightly coupled three-dimensional wiring structure that exhibits resonant behavior at the upper part of the spectrum. Consequently, in addition to the inductive and capacitive coupling, present between adjacent wires across the entire frequency bandwidth, distributed electromagnetic effects, manifested as interconnect-induced delay, reflection, radiation, and long-range nonlocal coupling, become prominent at high frequencies, with a decisive impact of overall system performance. The electromagnetic nature of such high-frequency effects, combined with the geometric complexity of the interconnect structure, make the electrical design of today's performance-driven systems extremely challenging. Its success is heavily dependent on the availability of sophisticated electromagnetic modeling methodologies and computer-aided design tools. This paper presents an overview of the different approaches employed today for the development of an electromagnetic modeling and simulation framework that can effectively tackle the complexity of the interconnect circuit and facilitate its design. In addition to identifying the current state of the art, an assessment is given of the challenges that lie ahead in the signal integrity-driven electrical design of tomorrow's performance- and/or portability-driven, multifunctional ULSI systems.

Progress in the methodologies for the electrical modeling of interconnects and electronic packages

Modeling of electromagnetic absorption/scattering problems using hp-adaptive finite elements

The authors propose and analyze the traveling-wave photodetector (TWPD), an edge-coupled photodetector that is capable of both a larger absolute bandwidth and a larger bandwidth-efficiency product than the waveguide photodetector (WGPD). The intrinsic RC bandwidth limitation is increased in the traveling-wave photodetector by providing for controlled transmission of the electrical wave down the device in parallel with the optical wave and by eliminating bandwidth-limiting electrical reflections. It is shown that 1- mu m wide, parallel-plate, GaAs/AlGaAs, p-i-n TWPD with open-circuit input termination has a 26% greater potential bandwidth-efficiency product than the comparable WGPD, while a TWPD with matched input termination actually has a worse bandwidth-efficiency product than the WGPD. >

Traveling-wave photodetectors

A highly accurate quasi-static model of a microstrip over a semiconductor layer has been developed. The model agrees with full-wave calculations in all three modes of propagation (skin-effect, slow-wave, and dielectric quasi-TEM), for both the attenuation constant alpha and the propagation constant beta over a very wide range of dimension, substrate conductivity, and frequency. To achieve this level of agreement, a nonuniform cross-section, transverse resonance technique has been applied to find the series impedance per unit length of the microstrip transmission line. >

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Highly accurate quasi-static modeling of microstrip lines over lossy substrates

A new approximation technique to find the total series impedance per unit length for quasi-TEM transmission lines including conductor loss has been developed. It is shown through the use of conformal mapping that both frequency dependent skin-depth and proximity effects can be accurately modeled. Comparison between experimental measurements and calculations for twin-lead, coplanar strips, parallel square bars, and coplanar waveguide all show excellent agreement. This technique is easily generalized to any transmission line making use of polygonal cross-section conductors. >

Quasi-static conductor loss calculations in transmission lines using a new conformal mapping technique

In this paper we apply the current filament method to surface "ribbons" instead of volume filaments, leading to a substantial reduction in problem size and increase in computational efficiency. The accuracy is excellent when compared to "full Weeks" calculations, with a factor of almost 100 reduction in CPU time.

Interconnect series impedance determination using a surface ribbon method

A circuit interconnection structure for synchronizing a network of oscillators placed on a semiconductor substrate. One such structure comprises a first synchronizing circuit electrically coupled to a second synchronizing circuit through tunable delay circuits. Also disclosed are methods to tune oscillators placed in different regions of a circuit having multiple clock domains by estimating the relative slack of a first group of signals within the circuit with regard to the period of a first clock domain, and estimating the relative slack of the second group of signals within the circuit with regard to the period of second clock domain, wherein the estimating is performed at process and operational corners that cover the variability of the circuit at different speed conditions, then calculating tuning values for the oscillator delays for each region such that the oscillator delay slack matches the worst relative slack of the signals of the same region.

Network of tightly coupled performance monitors for determining the maximum frequency of operation of a semiconductor IC

A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.

Emre Tuncer

Papers

Highly accurate quasi-static modeling of microstrip lines over lossy substrates

Quasi-static conductor loss calculations in transmission lines using a new conformal mapping technique

Interconnect series impedance determination using a surface ribbon method

Network of tightly coupled performance monitors for determining the maximum frequency of operation of a semiconductor IC

A variability-aware scheme for asynchronous circuit initialization