E
Erik Fischer
Researcher at Dresden University of Technology
Publications - 10
Citations - 155
Erik Fischer is an academic researcher from Dresden University of Technology. The author has contributed to research in topics: Queueing theory & Design space exploration. The author has an hindex of 7, co-authored 10 publications receiving 148 citations.
Papers
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Proceedings ArticleDOI
10.7 A 105GOPS 36mm 2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS
Benedikt Noethen,Oliver Arnold,Esther P. Adeva,Tobias Seifert,Erik Fischer,Steffen Kunze,Emil Matus,Gerhard Fettweis,Holger Eisenreich,Georg Ellguth,Stephan Hartmann,Sebastian Hoppner,Stefan Schiefer,Jens-Uwe Schlüßler,Stefan Scholze,Dennis Walter,Rene Schuffny +16 more
TL;DR: A heterogeneous MPSoC platform (Tomahawk2) with runtime scheduling and fine-grained hierarchical power management, which can fully adapt to the dynamically varying workload and semi-deterministic behavior in modern concurrent wireless applications is presented.
Proceedings ArticleDOI
Wireless interconnect for board and chip level
TL;DR: Within this paper approaches and results for building this infrastructure for future electronics are addressed and how to efficiently design the communications infrastructure which will be within electronic systems is addressed.
Proceedings ArticleDOI
A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications
Sebastian Haas,Tobias Seifert,Benedikt Nothen,Stefan Scholze,Sebastian Hoppner,Andreas Dixius,Esther P. Adeva,Thomas R. Augustin,Friedrich Pauls,Sadia Moriam,Mattis Hasler,Erik Fischer,Yong Chen,Emil Matus,Georg Ellguth,Stephan Hartmann,Stefan Schiefer,Love Cederstrom,Dennis Walter,Stephan Henker,Stefan Hanzsche,Johannes Uhlig,Holger Eisenreich,Stefan Weithoffer,Norbert Wehn,Rene Schuffny,Christian Mayr,Gerhard Fettweis +27 more
TL;DR: A heterogeneous SDR MPSoC with a hexagonal network-on-chip to address issues of latency, reliability, and flexibility and outperforms state-of-the-art platforms in terms of throughput.
Proceedings ArticleDOI
An accurate and scalable analytic model for round-robin arbitration in network-on-chip
Erik Fischer,Gerhard Fettweis +1 more
TL;DR: An accurate service time estimation model that is designed for round-robin arbiters is proposed and employed to a queueing model for network-on-chip and a comparison with cycle-accurate simulation proves the accuracy of the proposed service time model.
Proceedings ArticleDOI
Fair rate packet arbitration in Network-on-Chip
TL;DR: Two new arbitration techniques to enable fair link bandwidth allocation are proposed, one of which is a weighted round-robin scheme with weights based on the number of contending flows at the input port and the second an age-based scheme with probabilistic arbitration where the traversed packet distance approximates age.