Sadia Moriam

TL;DR: A heterogeneous SDR MPSoC with a hexagonal network-on-chip to address issues of latency, reliability, and flexibility and outperforms state-of-the-art platforms in terms of throughput.

TL;DR: This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS that integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling.

TL;DR: The proposed NoCManager employs a novel trellis-search-algorithm (TESSA) that solves the allocation optimization problem by making use of dynamic programming approach and achieves up to 8x higher allocation speed and up to 29 percent higher success rate against recently proposed distributed solution.

TL;DR: This paper investigates the hexagonal on-chip network topology with redundant diagonal inter-router links, having approximately 1.5 times the number of links as the mesh topology, and presents deadlock-free fault tolerant routing algorithms obtained by applying the turn model and without the use of costly virtual channels.

TL;DR: This paper addresses active attacks on NoCs, and uses network coding for the transmission of data in order to increase efficiency and robustness and analyzes the area overhead using a state-of-the-art MPSoC to demonstrate that the integrity of data can be protected with reasonable effort.