A 64-channel 0.13- $\mu \text{m}$ CMOS system on a chip (SoC) for neuroelectrical monitoring and responsive neurostimulation is presented. The $\Delta \Sigma $ -based neural channel records signals with rail-to-rail dc offset at the input without any area-intensive dc-removing passive components, which leads to a compact 0.013-mm2 integration area of recording and stimulation circuits. The channel consumes 630 nW, yields a signal to noise and distortion ratio of 72.2 dB, a 1.13- $\mu $ Vrms integrated input-referred noise over 0.1–500 Hz frequency range, and a noise efficiency factor of 2.86. Analog multipliers are implemented in each channel with minimum additional area cost by reusing the multi-bit current-digital to analog converter that is originally placed for current-mode stimulation. The multipliers are used for compact implementation of bandpass finite impulse response filters, as well as voltage gain scaling. A tri-core low-power DSP conducts phase-synchrony-based neurophysiological event detection and triggers a subset of 64 programmable arbitrary-waveform current-mode stimulators for subsequent neuromodulation. Two ultra-wideband (UWB) wireless transmitters communicate to receivers located at 10 cm to 2 m distance from the implanted SoC with data rates of 10–46 Mb/s, respectively. An inductive link that operates at 1.5 MHz provides power to the SoC and is also used to communicate commands to an on-chip ASK receiver. The chip occupies 6 mm2 while consuming 1.07 and 5.44 mW with delay-based and voltage controlled oscillator-based UWB transmitters, respectively. The SoC is validated in vivo using epilepsy monitoring (seizure detection) and treatment (seizure suppression) experiments.

Rail-to-Rail-Input Dual-Radio 64-Channel Closed-Loop Neurostimulator

A wireless and battery-less trimodal neural interface system-on-chip (SoC), capable of 16-ch neural recording, 8-ch electrical stimulation, and 16-ch optical stimulation, all integrated on a 5 ×  3 mm2 chip fabricated in 0.35-μm standard CMOS process. The trimodal SoC is designed to be inductively powered and communicated. The downlink data telemetry utilizes on–off keying pulse-position modulation (OOK-PPM) of the power carrier to deliver configuration and control commands at 50 kbps. The analog front-end (AFE) provides adjustable mid-band gain of 55–70 dB, low/high cut-off frequencies of 1–100 Hz/10 kHz, and input-referred noise of 3.46 μVrms within 1 Hz-50 kHz band. AFE outputs of every two-channel are digitized by a 50 kS/s 10-bit SAR-ADC, and multiplexed together to form a 6.78 Mbps data stream to be sent out by OOK modulating a 434 MHz RF carrier through a power amplifier (PA) and 6 cm monopole antenna, which form the uplink data telemetry. Optical stimulation has a switched-capacitor based stimulation (SCS) architecture, which can sequentially charge four storage capacitor banks up to 4 V and discharge them in selected μLEDs at instantaneous current levels of up to 24.8 mA on demand. Electrical stimulation is supported by four independently driven stimulating sites at 5-bit controllable current levels in ±(25–775) μA range, while active/passive charge balancing circuits ensure safety. In vivo testing was conducted on four anesthetized rats to verify the functionality of the trimodal SoC.

A Trimodal Wireless Implantable Neural Interface System-on-Chip

We present a bidirectional neural interface with a 4-channel biopotential analog-to-digital converter (bioADC) and a 4-channel current-mode stimulator in 180 nm CMOS. The bioADC directly transduces microvolt biopotentials into a digital representation without a voltage-amplification stage. Each bioADC channel comprises a continuous-time first-order $\Delta \Sigma$ modulator with a chopper-stabilized OTA input and current feedback, followed by a second-order comb-filter decimator with programmable oversampling ratio. Each stimulator channel contains two independent digital-to-analog converters for anodic and cathodic current generation. A shared calibration circuit matches the amplitude of the anodic and cathodic currents for charge balancing. Powered from a 1.5 V supply, the analog and digital circuits in each recording channel draw on average $\text{1.54}\; \mu {\rm A}$ and $\text{2.13} \;\mu {\rm A}$ of supply current, respectively. The bioADCs achieve an SNR of $\text{58 dB}$ and a SFDR of ${>} \text{70 dB}$ , for better than 9-b ENOB. Intracranial EEG recordings from an anesthetized rat are shown and compared to simultaneous recordings from a commercial reference system to validate performance in-vivo . Additionally, we demonstrate bidirectional operation by recording cardiac modulation induced through vagus nerve stimulation, and closed-loop control of cardiac rhythm. The micropower operation, direct digital readout, and integration of electrical stimulation circuits make this interface ideally suited for closed-loop neuromodulation applications.

A Bidirectional Neural Interface IC With Chopper Stabilized BioADC Array and Charge Balanced Stimulator

Implantable closed-loop neural stimulation is desirable for clinical translation and basic neuroscience research. Neural stimulation generates large artifacts at the recording sites, which saturate existing recording front ends. This paper presents a low-power continuous-time delta-sigma analog to digital converter (ADC), which along with an 8 $\times $ gain capacitively-coupled chopper instrumentation amplifier (CCIA), realizes a front end that can digitize neural signals from 1 Hz to 5 kHz in the presence of 200-mVpp differential artifacts and 700-mVpp common-mode (CM) artifacts. A modified loop-filter is used in the ADC along with new linearization techniques to significantly reduce power consumption. Fabricated in 40-nm CMOS, the ADC occupies an area of 0.053 mm2, consumes 4.5 $\mu \text{W}$ from a 1.2-V supply, has an input impedance of 20 $\text{M}\Omega $ and bandwidth (BW) of 5 kHz, and achieves a peak signal to noise and distortion ratio (SNDR) of 93.5 dB for a 1.77- $\text{V}_{\mathrm {pp}}$ differential input at 1 kHz. The ADC’s figure of merit (FOM) (using SNDR) is 184 dB, which is 6 dB higher than the state of the art in high-resolution ADCs. The complete front end occupies an area of 0.113 mm2, consumes 7.3 $\mu \text{W}$ from a 1.2-V supply, has a dc input impedance of 1.5 $\text{G}\Omega $ , input-referred noise of 6.35 $\mu \text{V}_{\mathrm {rms}}$ in 1 Hz–5 kHz, and total harmonic distortion of −81 dB for a 200-mVpp input at 1 kHz, and is immune to 700-mVpp CM interference. Compared to front ends intended for closed-loop neural recording, this paper improves the linear input range by 2 $\times $ , the signal BW by 10 $\times $ , the dynamic range by 12.6 dB, the FOM by 12.4 dB and remains immune to large CM interference while maintaining comparable power, area, and noise performance.

A 15.2-ENOB 5-kHz BW 4.5- $\mu$ W Chopped CT $\Delta\Sigma$ -ADC for Artifact-Tolerant Neural Recording Front Ends

A low-power fully-integrated analog front end for biopotential sensors is proposed. The signal conditioning circuitry features an integrating sampler and a digital-assisted electrode offset-cancellation loop. The chip is fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. The supply voltage is 1.2 V and the quiescent current is $7.7~\mu \text{A}$ . Measurement results show that the analog front end achieves an in-band gain of 58 dB, a noise spectrum density of 46nV/ $\sqrt {\text{Hz}} $ and can tolerate ±60 mV electrode offset. The THD is below 1% with a 2mVpp input. The analog signal is converted to digital code at 5kS/s by a 12-bit SAR ADC with 63.2 dB SNDR. The prototype IC is experimented with capturing ECG on human beings.

A Fully Integrated Analog Front End for Biopotential Signal Sensing

We present a 4-channel integrated biopotential analog-to-digital converter (bioADC) for electrocortical recording in 180nm CMOS. The bioADC directly transduces microvolt biopotentials into a digital representation without a voltage-amplification stage. Each channel comprises a continuous-time first-order ΔΣ modulator with OTA input and current feedback, followed by a second-order comb-filter decimator. Powered from a 1.5V supply, the analog and digital circuits in each channel draw 2.1uA and 1.4uA of supply current, respectively. The bioADCs achieve an SNR of 57dB and a SFDR or 63.5dB, for 9-b ENOB. Intracranial EEG recordings from an anesthetized rat are shown and compared to simultaneous recordings from a commercial reference system to validate performance in-vivo. The micropower operation and direct digital readout make this circuit ideally suited for closed-loop neuromodulation applications.

A 5 μW/channel 9b-ENOB BioADC array for electrocortical recording

Single modality wireless power transfer has limited depth for mm-sized implants across air/tissue or skull/tissue interfaces because they either suffer from a high loss in tissue (RF, optical) or high reflection at the medium interface [ultrasound (US)]. This article proposes an RF-US relay chip at the media interface avoiding the reflection at the boundary and enables efficient wireless powering to mm-sized deep implants across multiple media. The relay chip rectifies the incoming RF power through an 85.5% efficient RF inductive link (across air) using a multi-output regulating rectifier (MORR) with 81% power conversion efficiency (PCE) at 186 mW load and transmits using adiabatic power amplifiers (PAs) to the implant in order to minimize cascaded power loss. To adapt US focus to implant movement or placement, beamforming was implemented using six channels of US PAs with two-bit phase control (0°, 90°, 180°, and 270°) and three different amplitudes (6–29, 4.5, and 1.8 V) from the MORR. The adiabatic PA contributes a 30%–40% increase in efficiency over class-D and beamforming increases the efficiency by 251% at 2.5 cm over fixed focusing. The proof-of-concept powering system for a retinal implant, from an external PA on a pair of glasses to a hydrophone with 1.2 cm (air) + 2.9 cm (agar eyeball phantom in mineral oil) separation distance, had a power delivered to the load (PDL) of 946 $\mu \text{W}$ . The 2.3 mm × 2 mm relay chip was fabricated in a 180 nm high-voltage (HV) BCD process.

Ernest So

Papers

A Bidirectional Neural Interface IC With Chopper Stabilized BioADC Array and Charge Balanced Stimulator

A 5 μW/channel 9b-ENOB BioADC array for electrocortical recording

An RF-Ultrasound Relay for Adaptive Wireless Powering Across Tissue Interfaces