An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

An electrically programmable low impedance circuit element is disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming The electrically programmable low impedance circuit element of the present invention includes a lower conductive electrode which may be formed of a metal or semiconductor material, an insulating layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide An upper electrode formed of a metal or of a semiconductor material of the same conductivity type of the lower electrode or a sandwich of both completes the structure

Programmable low-impedance anti-fuse element

A nitride programmable read only memory (NROM) cell with a pocket implant self-aligned to at least one bit line junction. Alternatively, the bit line junction(s) can have a thin area of effective programming and erasing located nearby. Further alternatively, the channel can have a threshold voltage level implant which has a low voltage level in a central area of the channel and which has a peak of high voltage level near at least one of the bit line junctions. With one pocket implant, the NROM cell stores one bit. With two pocket implants, the NROM cell stores two bits.

NROM cell with improved programming, erasing and cycling

A method of fabricating a nitride read only memory (NROM) chip creates an oxide-nitride-oxide (ONO) layer on a substrate and etches the ONO layer within the memory portion of the chip into columns. Bit lines are implanted between columns after which bit line oxides are generated on top of the bit lines with the thickness of the bit line oxides being independent of the thickness of the bottom oxide. The thickness of a gate oxide layer in a periphery portion of the chip is also relatively independent of the thicknesses of the other oxides. Finally, rows of polysilicon or polysilicide are formed perpendicular to and on top of the bit line oxides and the ONO columns.

NROM fabrication method with a periphery portion

Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath. At least one of the two electrodes of each anti-fuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer. This arsenic will combine with other material and flow into the anti-fuse filament after programmed to form a low resistance controllable anti-fuse link. Circuitry is provided which allows the anti-fuse of the present invention to be programmed by application of a suitable programming voltage to input-output pins of the integrated circuit containing the antifuse. Where more than one anti-fuse is to be programmed using the programming voltage applied at the input-output terminals, other additional input-output terminals may serve as address inputs to specify the anti-fuse to be programmed.

Electrically-programmable low-impedance anti-fuse element

An integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of multi-layer insulating layer comprised of a storage layer and a "blocking" layer. The "blocking" layer consists of an oxynitride layer formed by oxidation of a silicon nitride layer surface or an additionally applied SiO2 layer and has a layer thickness of about 5 to 30 nm. Such "blocking" layer prevents an undesired injection of charge carriers from the silicon-gate electrode. It also provides means for forming a self-adjusting, overlapping polysilicon contact.

Process for producing an integrated multi-layer insulator memory cell

A method for manufacturing MNOS memory transistors with very short channel lengths in silicon gate technology. In a substrate of a first semiconductor type, source and drain zones of MNOS and MOS components of a second conductivity type opposite the first conductivity type are provided. The edges of gate electrodes, with reference to the plane of the substrate surface, lie perpendicularly and self-adjusting over the edges of the source and drain zones, whereby the source and drain zones generated in the substrate are manufactured by means of ion implantation upon employment of the gate electrodes as the implantation mask.

Method of making very short channel length MNOS and MOS devices by double implantation of one conductivity type subsequent to other type implantation

A method for the manufacture of LSI complementary MOS field effect transistor circuits to increase the latch-up hardness of the n-channel and p-channel field effect transistors while retaining good transistor properties by incorporating a further epitaxial layer and highly doped implantation regions into a lower epitaxial layer from which the wells are generated by out-diffusion into the upper epitaxial layer. In addition to achieving optimum transistor properties, the reduced lateral diffusion provided enables a lower n+ /p+ spacing, and thus achieves a higher packing density with improved latch-up hardness.

Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing

OF THE DISCLOSURE Integrate MOS circuits with and without MNOS transistors in silicon-gate technology are produced with overlapped contacts using a silicon nitride mask. After production of structured SiO2 layer on a p- or n- doped semiconductor substrate to separate active transistor zones in accordance with the so-called LOCOS process, a silicon nitride layer is deposited onto the surface and is then structured so that the zones in which a gate oxide is to be produced, are uncovered and during gate oxidation, the surface of this structured silicon nitride layer is converted into an oxynitride layer. In contrast to previously known processes, the invention provides self-aligned overlapped contacts with oversized contact holes. The silicon-nitride layer functions as an etch-stop during etching of an intermediate oxide. This avoids under-etching of the polysilicon during contact hole etching. The overlapped contacts allow a substantial increase in the packing and integra-tion density of the so-produced circuits.

Process for production of integrated mos circuits with and without mnos memory transistors in silicon-gate technology

The invention provides a method for manufacturing adjacent tubs implanted with dopant material ions in the manufacture of LSI complementary MOS field effect transistor circuits (CMOS circuits), and also provides a method sequence for a CMOS process adapted to tub manufacture. In accordance with the principles of the invention, for the greatest possible spatial separation of the tubs, a p-tub (5) is produced before a n-tub (8) and an undercutting (25) of a nitride layer (4) serving as the implantation mask in the p-tub production is intentionally produced, so that, during a subsequent oxidation, the edge of the oxidation is shifted toward the outside by about 1 to 2 μm. Further, the penetration depth x jn of the n-tub (8) is set smaller by a factor at least equal to 4 relative to the penetration depth x jp of the p-tub (5), whereby the thickness of the n-doped epitaxial layer (2) and the penetration depth x jp are about matched to one another. The two tubs are separately implanted and diffused. As a result of the inventive sequences, the disadvantages of mutual, extensive compensation of the p-tub and the n-tub are avoided.

Erwin Jacobs

Papers

Process for producing an integrated multi-layer insulator memory cell

Method of making very short channel length MNOS and MOS devices by double implantation of one conductivity type subsequent to other type implantation

Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing

Process for production of integrated mos circuits with and without mnos memory transistors in silicon-gate technology

Process for producing adjacent tubs implanted with dopant ions in the manufacture of LSI complementary MOS field effect transistors