The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Tri-gate devices and methods of fabrication

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

Nonplanar transistors with metal gate electrodes

A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top surface opposite a bottom surface formed above an insulating substrate wherein the semiconductor body has a pair laterally opposite sidewalls. A gate dielectric is formed on the top surface of the semiconductor body on the laterally opposite sidewalls of the semiconductor body and on at least a portion of the bottom surface of semiconductor body. A gate electrode is formed on the gate dielectric, on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of semiconductor body and beneath the gate dielectric on the bottom surface of the semiconductor body. A pair source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication

An integrated circuit containing bipolar and complementary MOS transistors wherein the emitter terminals of the bipolar transistors as well as the gate electrodes of the MOS transistors are composed of the same material, consisting of a metal silicide or of a double layer containing a metal silicide and a polysilicon layer. The emitter base terminals are arranged in self-adjusting fashion relative to one another and the collector is formed as a buried zone. The collector terminal is annularly disposed about the transistor. As a result of the alignment in dependent spacing between the emitter and the base contact, the base series resistance is kept low and a reduction of the space requirement is achieved. The doping of the bipolar emitter and of the n-channel source/drain occurs independently. The method for the manufacture of the integrated circuit employs an n-doped gate material of the MOS transistors as a diffusion source and as a terminal for the emitters of the bipolar transistors and does not require an additional photolithography step. Because of the annular, deep collector region, a reduction of the collector series resistance and an increased latch-up hardness are achieved. The integrated semiconductor circuit is employed in VLSI circuits having high switching speeds.

Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate

A method for the manufacture of LSI complementary MOS field effect transistor circuits to increase the latch-up hardness of the n-channel and p-channel field effect transistors while retaining good transistor properties by incorporating a further epitaxial layer and highly doped implantation regions into a lower epitaxial layer from which the wells are generated by out-diffusion into the upper epitaxial layer. In addition to achieving optimum transistor properties, the reduced lateral diffusion provided enables a lower n+ /p+ spacing, and thus achieves a higher packing density with improved latch-up hardness.

Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing

A method for the manufacture of integrated MOS-field effect transistor circuits in silicon gate technology and wherein diffusion source and drain zones are coated with a high melting point silicide as low-impedance printed conductors. The diffusion zones and polysilicon gates are made low-impedance through selective deposition of the metal silicide onto surfaces thereof. The selective deposition, which proceeds by use of a reaction gas eliminating hydrogen halide, simplifies the process sequence and is fully compatible with conventional silicon gate processes. Because of the high temperature stability, preferably tantalum silicide is employed. The invention is useful in the manufacture of MOS-circuits in VLSI-technology.

Method for the manufacture of integrated MOS-field effect transistor circuits silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors

A FET, in which a channel region is formed in a bridge (4) etched from the silicon layer of the SOI substrate, which bridge is enclosed in the manner of a bracket by a gate metallisation (5), a dielectric layer (6) being present between the gate metallisation (5) and the bridge (4) and the source and drain regions being provided by doping (7) in order to form a MOSFET.

MOSFET on SOI substrate

The invention relates to a method for producing MOS transistors with flat source/drain zones, short channel lengths, and a self aligned contacting plane comprised of a metal silicide. In this method, the source/drain zones in the semiconductor substrate are produced by out-diffusion of the contacting plane consisting of a doped metal silicide and deposited directly on the substrate. The method serves to produce NMOS, PMOS, and in particular CMOS circuits in VLSI technology and permits a very high packing density and an independent additional wiring plane of very low resistance.

Franz Dr. Rer. Nat. Neppl

Papers

Method of manufacturing integrated circuit containing bipolar and complementary MOS transistors on a common substrate

Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing

Method for the manufacture of integrated MOS-field effect transistor circuits silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors

MOSFET on SOI substrate

Method of making MOS device using metal silicides or polysilicon for gates and impurity source for active regions